Design & Reuse
Partner Highlight

New Products

Alphacore, Inc.
12-bit, 500 MSPS, Digital-to-Analog Converter (ADC), IP block, TSMC 12nm
Kudelski Labs
Kudelski Labs keySTREAM
Dolphin Semiconductor
24-bit Cap-less ADC with 101 dB SNR, offering low power consumption and low latency, supporting 1 channel (mono) in TSMC 12FFC.
Dnotitia
VDPU (Vector Data Processing Unit)
NTLab
180SMIC_LPF_05 - 1 to 200 MHz Low-pass filter with frequency adjustment system

Blogs

Light-speed ambition: GlobalFoundries acquires AMF and InfiniLink to power the AI datacenter revolution
Kevin Soukup
GlobalFoundries
How Time Sensitive Networking powers the Software Defined Vehicle
Comcores
Comcores
Maximizing SoC Longevity with PCIe 3.0: A Designer’s Guide
Key ASIC
Key ASIC
Key ASIC
Let's Visit the Zoo
Quadric
Quadric
Quadric
Powering the future: Why GF’s new agreement with TSMC is supercharging GaN innovation
Téa Williams
GlobalFoundries
ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
KiviCore
KiviCore
Why anti-tamper sensors matter
Agile Analog
Raj Uppala, Rambus
Agile Analog
Fortune & Great Place To Work Name Cadence to 2025 World’s Best Workplaces List
Cadence Design Systems, Inc.
Cadence Design Systems, Inc.
New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug
Cadence Design Systems, Inc.
Cadence Design Systems, Inc.
Industrial gateway for IO-Link to build smarter connectivity
MosChip Technologies, USA
Ambuj Nandanwar
MosChip Technologies, USA
A Shared Commitment to Energy-Efficient AI
TSMC
Aveek Sarkar
TSMC
10 Tips for First-Pass Silicon Success in AI Chip Development
Synopsys, Inc.
Frank Schirrmeister, Rita Horner, Todd Koelling
Synopsys, Inc.

Articles

Three Ethernet Design Challenges in Industrial Automation
Key ASIC
Key ASIC
ST silicon photonics and BiCMOS technologies: the winning portfolio for AI optical interconnects
STMicroelectronics
STMicroelectronics
AI in VLSI Physical Design: Opportunities and Challenges
Japesh Kumar, Qualcomm
AI-Driven and Traditional Approaches to Accident Scenario Reconstruction
Vayavya Labs
Nitin Swamy
Vayavya Labs
From Theory to the Field: Why Side-Channel Protection Defines Post-Quantum Security
PQSecure Technologies
PQSecure Technologies
PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
Innosilicon Technology Ltd
Innosilicon Technology Ltd
Design Approaches and Architectures of RISC-V SoCs
Maven Silicon
Maven Silicon
Implementation of Metal ECO using Mask Programmable Cell for Hold Timing Violations
eInfochips, Inc.
Dhanyakumar Shah,Dharmik Lakhani
eInfochips, Inc.
Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
Menta
Menta
Bridging Design Verification Gaps with Formal Verification
Karim Waseem, Si-vision
Post-Quantum Cryptography: Why Open Source alone is Not Enough for Secure IP Deployment
PQSecure Technologies
Dr. Reza Azarderakhsh
PQSecure Technologies
The Blind Spot of Semiconductor IP Sales
CoreHW
Petri Heliö, Principal IC Designer
CoreHW
Today on Design And Reuse

bullet_arrow  SAICEC Partners with Siemens to Accelerate Chip-to-vehicle Validation - December 1, 2025

bullet_arrow  EU digital package promises €155B in savings with streamlined AI and data rules - November 28, 2025

bullet_arrow  Sovereign AI: The New Foundation of National Power - November 28, 2025

bullet_arrow  Intel Could Manufacture Apple M-Series Chips in 2027 with 18A-P Node - November 28, 2025

bullet_arrow  BOS Semiconductors Eyes Expansion into ‘Intelligent Space’ AI Market Beyond ADAS - November 27, 2025

bullet_arrow  Edge AI’s Next Battlefield: Development Tools - November 27, 2025

Partner Highlight
Latest News Alerts