LiteX-M2SDR is an open-source Software Defined Radio platform that combines an Analog Devices AD9361 RFIC with a Xilinx Artix-7 XC7A200T FPGA in a compact M.2 2280 form factor. The project provides a complete SDR solution spanning hardware design, FPGA gateware, Linux kernel drivers, and application-level software.
LiteX-M2SDR is designed for SDR enthusiasts, FPGA developers, and researchers who need a flexible, open-source radio platform with high-bandwidth connectivity and extensive processing capabilities. The platform leverages the LiteX framework for FPGA gateware generation, enabling efficient HDL coding and rapid system integration.
Key Distinguishing Features:
Sources: README.md1-60 README.md35-48 </old_str>
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The LiteX-M2SDR system is organized into three primary layers that work together to provide complete SDR functionality:
The physical board contains the FPGA, AD9361 RFIC, SI5351 clock generator, and SPI flash for configuration storage. The M.2 connector provides either direct PCIe connectivity (when installed in an M.2 slot) or can be mounted on the optional LiteX Acorn Baseboard for Ethernet and SATA access via the GTP transceivers.
See page 1.2 for complete hardware specifications.
The FPGA gateware is built using the LiteX framework with Python/Migen. The BaseSoC class litex_m2sdr.py150-196 orchestrates all components:
Data flows through LiteX stream endpoints using standardized dma_layout(64) format for 64-bit paths. The stream crossbar litex_m2sdr.py561-591 enables flexible routing between any communication interface and the AD9361.
See page 3 for detailed gateware architecture and page 1.1 for system architecture details.
The software stack provides multiple access paths:
m2sdr.ko): Manages PCIe/DMA operations, interrupt handling, and device nodes software/kernel/liblitepcie, libm2sdr, libad9361_m2sdr provide C APIs for hardware access software/user/m2sdr_util, m2sdr_rf, m2sdr_record/playSee page 4 for complete software stack documentation.
Sources: README.md116-134 litex_m2sdr.py150-196 litex_m2sdr.py544-591 </old_str> <new_str>
| Component | Specification | Details |
|---|---|---|
| RF Frontend | AD9361 RFIC | 70 MHz - 6 GHz coverage, 2T2R configuration |
| Sample Rate | 61.44 MSPS standard | 122.88 MSPS oversampling mode (requires PCIe x2/x4) |
| Sample Resolution | 12-bit I/Q | Per channel, dual channels per direction |
| FPGA | XC7A200TSBG484-3 | Xilinx Artix-7, ~50% base utilization |
| Form Factor | M.2 2280 | 22mm × 80mm, fits standard M.2 slots |
| Clock Generator | SI5351B or SI5351C | B: VCXO mode, C: External 10MHz reference |
| Flash Storage | Quad-SPI | Multiboot support for safe remote updates |
| Connectivity | PCIe Gen2 x1/x2/x4 | Up to ~14 Gbps bandwidth |
| Ethernet 1G/2.5G | Via baseboard (1000BaseX/2500BaseX) | |
| SATA Gen1/2 | Via baseboard (in development) |
Hardware Variants:
For detailed hardware specifications, see page 1.2.
Sources: README.md10-14 README.md79-84 litex_m2sdr_platform.py185-189
LiteX-M2SDR is an M.2 2280 form-factor Software Defined Radio built around the Analog Devices AD9361 RFIC and Xilinx XC7A200T Artix-7 FPGA. The design is implemented using the LiteX framework, providing a complete SDR solution with integrated gateware, kernel drivers, and user-space software.
| Component | Specification |
|---|---|
| RF Frontend | AD9361 RFIC (70 MHz - 6 GHz) |
| Configuration | 2T2R (2 transmit, 2 receive channels) |
| Sample Rate | 61.44 MSPS (standard), 122.88 MSPS (oversampling) |
| Sample Resolution | 12-bit I/Q samples |
| FPGA | Xilinx XC7A200T Artix-7 (speedgrade -3) |
| FPGA Resources | ~50% utilized by base design |
| Form Factor | M.2 2280 (22mm × 80mm) |
| Clock Generator | SI5351B (VCXO) or SI5351C (external reference) |
| Interface | Specification | Use Case |
|---|---|---|
| PCIe | Gen 2 x1/x2/x4 (~4/8/14 Gbps) | High-bandwidth streaming |
| Ethernet | 1000BaseX / 2500BaseX | Remote/distributed operation |
| SATA | Gen 1/2/3 (WIP) | Direct SSD recording |
Sources: README.md10-14 litex_m2sdr_platform.py185-189 litex_m2sdr.py198-206
LiteX-M2SDR supports diverse operating modes and features that can be configured at build time:
| Feature Category | Capability | Configuration | Notes |
|---|---|---|---|
| RF Operation | 2T2R SDR | Always enabled | Full duplex operation |
| Standard Mode | 61.44 MSPS | Default configuration | |
| Oversampling | 122.88 MSPS | Requires PCIe x2/x4 | |
| Connectivity | PCIe | Gen2 x1/x2/x4 | --with-pcie --pcie-lanes=N |
| Ethernet | 1G/2.5G | --with-eth (baseboard only) | |
| SATA | Gen1/2/3 | --with-sata (WIP, baseboard only) | |
| Timing/Sync | Internal Time | 64-bit ns counter | Always available |
| PCIe PTM | ~50ns accuracy | --with-pcie-ptm (x1 only) | |
| White Rabbit | Sub-ns network sync | --with-white-rabbit (baseboard) | |
| External Ref | 10MHz input | SI5351C variant only | |
| Data Paths | Zero-Copy DMA | PCIe streaming | High throughput |
| UDP Streaming | Ethernet RX/TX | RX working, TX in development | |
| Direct Recording | SATA to SSD | In development | |
| Software | C API | Low-level control | Command-line utilities |
| SoapySDR | Standard API | GQRX, GNU Radio compatible |
For complete capability matrix and deployment configurations, see page 8.
Sources: README.md86-115 litex_m2sdr.py864-950
LiteX-M2SDR supports multiple deployment configurations optimized for different use cases:
Insert the M.2 board directly into a PCIe M.2 slot on x86 desktops, servers, or ARM platforms (Raspberry Pi 5, OrangePi 5 Max, NVIDIA Jetson). This configuration provides:
Build command: ./litex_m2sdr.py --with-pcie --pcie-lanes=4 --variant=m2 --build
See pages 8.1, 8.2, and 8.3 for platform-specific setup guides.
Mount the M.2 board on the LiteX Acorn Baseboard to access additional connectivity:
Build command: ./litex_m2sdr.py --with-eth --eth-sfp=0 --variant=baseboard --build
See page 8.4 for baseboard configuration details.
Deploy multiple LiteX-M2SDR boards in a multi-slot M.2 carrier with synchronized clocking:
Connect multiple boards via White Rabbit Ethernet switches:
Sources: README.md35-60 README.md116-152 doc/hosts/raspberry-pi-5.md1-10 doc/hosts/orangepi-5-max.md1-8
The quickest path to running LiteX-M2SDR depends on your use case:
Install prerequisite packages on Ubuntu/Debian:
Insert the board into an M.2 PCIe slot and connect antennas
Clone and build software:
Launch SDR applications: GQRX, GNU Radio, or other SoapySDR-compatible software will detect the LiteX-M2SDR device
See page 2 (Getting Started) for detailed installation instructions and troubleshooting.
After completing the SDR setup above:
m2sdr_util info, m2sdr_rf init, m2sdr_record/m2sdr_playliblitepcie, libm2sdr, libad9361_m2sdrSee page 4 (Software Stack) for API documentation.
Install LiteX following LiteX Wiki
Build and load custom gateware:
Use JTAGBone/PCIeBone for debugging:
See page 5 (Build System) and page 11 (Development Guide) for gateware development.
Sources: README.md153-209 README.md242-282
LiteX-M2SDR provides multiple software interfaces for different use cases:
The SoapyLiteXM2SDR driver software/soapy/ implements the standard SoapySDR API, enabling compatibility with:
Device discovery: SoapySDRUtil --probe="driver=LiteXM2SDR"
See page 4.4 for SoapySDR driver documentation.
Direct hardware control via C utilities software/user/:
m2sdr_util: Device information, DMA testing, capabilities querym2sdr_rf: AD9361 configuration (frequency, gain, sample rate, filters)m2sdr_record: Stream IQ samples to file (PCIe or Ethernet)m2sdr_play: Transmit IQ samples from filem2sdr_flash: Remote firmware update over PCIeSee page 4.3 for utility documentation and examples.
Low-level hardware access for custom applications:
liblitepcie: PCIe DMA operations, buffer management software/user/liblitepcie/libliteeth: UDP streaming, Etherbone protocol software/user/libliteeth/libm2sdr: SI5351 control, flash operations software/user/libm2sdr/libad9361_m2sdr: AD9361 configuration, FIR filters software/user/libad9361/See page 4.2 and page 10 for API reference.
Sources: README.md242-280 software/soapy/ software/user/
This wiki is organized into the following sections:
Page 1 (this page): Overview and introduction to LiteX-M2SDR
Page 2: Getting Started - Installation and quick start guides
Page 3: FPGA Gateware Design - BaseSoC, platform, clocking, AD9361 integration
Page 4: Software Stack - Kernel driver, libraries, utilities, SoapySDR driver
Page 5: Build System - Gateware and software build processes
Page 6: RF Configuration and Operation - AD9361, SI5351, GPIO control
Page 7: Data Streaming - Recording, playback, and streaming via different interfaces
Page 8: Deployment Scenarios - Platform-specific setup (x86, Raspberry Pi, etc.)
Page 9: Testing and Diagnostics - DMA testing, PRBS, debug tools
Page 10: API Reference - Complete CSR map and software API documentation
Page 11: Development Guide - Workflow, custom features, testing framework
For technical support and custom development inquiries, contact: florent@enjoy-digital.fr
Sources: README.md329-340
The Platform class litex_m2sdr_platform.py180-244 defines the physical hardware interface including I/O pins, connectors, and FPGA device configuration.
AD9361 RFIC Interface litex_m2sdr_platform.py104-134:
rx_clk_p/n: DDR LVDS receive clock (LVDS_25, DIFF_TERM)rx_frame_p/n: RX frame synchronization signalrx_data_p/n: 6 differential pairs for RX data (12-bit DDR)tx_clk_p/n: DDR LVDS transmit clocktx_frame_p/n: TX frame synchronization signaltx_data_p/n: 6 differential pairs for TX data (12-bit DDR)rst_n, enable, txnrx, en_agc: Control signalsctrl[3:0], stat[7:0]: Configuration interfaceSI5351 Clock Generator litex_m2sdr_platform.py28-38:
scl, sda: I2C control interface (LVCMOS33, PULLUP)ssen_clkin: Spread spectrum enable (B) / external clock input (C)pwm: VCXO tuning PWM outputsi5351_clk0: 40 MHz output to AD9361si5351_clk1: 100 MHz output to TimeGeneratorPCIe Connections litex_m2sdr_platform.py50-86:
m2 and baseboard variantsPETp/n (TX), PERp/n (RX)REFClkp/nGPIO Interface litex_m2sdr_platform.py137:
The platform configures the Artix-7 with quad-SPI flash support (4-bit @ 33 MHz) and multiboot capability litex_m2sdr_platform.py191-218
Sources: litex_m2sdr_platform.py14-177 litex_m2sdr_platform.py180-244
LiteX-M2SDR integrates seamlessly with the broader SDR software ecosystem through standardized interfaces:
The platform's design philosophy emphasizes openness and extensibility, allowing developers to implement custom RF processing algorithms directly in the FPGA while maintaining compatibility with existing SDR software tools.
Sources: README.md198-209 README.md140-142
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