Information for "SystemVerilog"
Basic information
| Display title | SystemVerilog |
| Default sort key | Systemverilog |
| Page length (in bytes) | 35,779 |
| Namespace ID | 0 |
| Page ID | 2540686 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of page watchers | 74 |
| Number of page watchers who visited in the last 30 days | 9 |
| Number of redirects to this page | 4 |
| Counted as a content page | Yes |
| Wikidata item ID | Q1387402 |
| Local description | Hardware description and hardware verification language |
| Central description | hardware description and hardware verification language |
| Page views in the past 30 days |
Page protection
| Edit | Allow all users (no expiry set) |
| Move | Allow all users (no expiry set) |
Edit history
| Page creator | 216.58.29.129 (talk) |
| Date of page creation | 01:22, 26 August 2005 |
| Latest editor | Greenbreen (talk | contribs) |
| Date of latest edit | 02:20, 18 December 2025 |
| Total number of edits | 429 |
| Recent number of edits (within past 30 days) | 0 |
| Recent number of distinct authors | 0 |