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[PATCH][PR target/122942] RISC-V: Add zifencei extension to the rva23s64 and rvb23s64...
authorPeter Bergner <bergner@tenstorrent.com>
Mon, 1 Dec 2025 23:03:44 +0000 (16:03 -0700)
committerJeff Law <jlaw@ventanamicro.com>
Mon, 1 Dec 2025 23:03:44 +0000 (16:03 -0700)
While verifying our Ascalon extensions list was complete (it isn't, follow-on
patch coming), I noticed that the rva23s64 and rvb23s64 profiles were missing
the mandatory zifencei extension, hence the following patch.

This was bootstrapped and regtested with no regressions.
Ok for trunk?

Peter

The RVA23S64 and RVB23S64 profiles both state that zifencei is a mandatory
extension.  Add it to both profiles.

gcc/
PR target/122942
* config/riscv/riscv-profiles.def (rva23s64): Add zifencei.
(rvb23s64): Likewise.

gcc/config/riscv/riscv-profiles.def patch | blob | history

diff --git a/gcc/config/riscv/riscv-profiles.def b/gcc/config/riscv/riscv-profiles.def
index 741c4719b37d616b59bbc9ea1c321cc7780be8b4..ea1c235a22c238dfb943f8e13db4c808712caa7e 100644 (file)
--- a/gcc/config/riscv/riscv-profiles.def
+++ b/gcc/config/riscv/riscv-profiles.def
@@ -61,7 +61,7 @@ RISCV_PROFILE("rva23s64",     "rv64imafdcbv_zicsr_zicntr_zihpm_ziccif_ziccrse"
                                 "_zicbom_zicbop_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl"
                                 "_zicond_zimop_zcmop_zcb_zfa_zawrs_svbare_svade_ssccptr"
                                 "_sstvecd_sstvala_sscounterenw_svpbmt_svinval_svnapot_sstc"
-                                "_sscofpmf_ssnpm_ssu64xl_sha_supm")
+                                "_sscofpmf_ssnpm_ssu64xl_sha_supm_zifencei")
 
 /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
    'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory extensions.  */
@@ -77,6 +77,6 @@ RISCV_PROFILE("rvb23s64",     "rv64imafdcb_zicsr_zicntr_zihpm_ziccif_ziccrse"
                                 "_zicbom_zicbop_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt"
                                 "_zihintntl_zicond_zimop_zcmop_zcb_zfa_zawrs_svbare_svade"
                                 "_ssccptr_sstvecd_sstvala_sscounterenw_svpbmt_svinval_svnapot"
-                                "_sstc_sscofpmf_ssu64xl_supm")
+                                "_sstc_sscofpmf_ssu64xl_supm_zifencei")
 
 #undef RISCV_PROFILE
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