boards: arm: add SMP variant for Corstone-1000-A320 FVP

Add an SMP variant (fvp_corstone1000/a320/smp) that enables all 4
Cortex-A320 CPUs on the Corstone-1000-A320 FVP.

Changes:
- Add board variant 'smp' with DTS, defconfig, and yaml
- Add PSCI node to dtsi (needed for PM_CPU_OPS_PSCI)
- Enable ENABLE_MULTICORE in both TF-M and TF-A sysbuild args
  so TF-M boots all 4 host CPUs and TF-A provides PSCI CPU_ON
- Add TF-A patch fixing secondary core hold pen cache coherency:
  BL2's dcsw_op_all during BL2-to-BL31 transition pushes stale
  cached data over WAIT values written by secondary CPUs from
  non-cached context

Tested with tests/kernel/smp on FVP_Corstone-1000-A320:
all 4 CPUs boot and all SMP test cases pass.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Author: Nicolas Pitre

boards/arm/fvp_corstone1000/Kconfig.fvp_corstone1000

@@ -3,3 +3,4 @@
 
 config BOARD_FVP_CORSTONE1000
 	select SOC_A320 if BOARD_FVP_CORSTONE1000_A320
+	select SOC_A320 if BOARD_FVP_CORSTONE1000_A320_SMP

boards/arm/fvp_corstone1000/board.cmake

@@ -106,6 +106,8 @@ if(CONFIG_BUILD_WITH_TFA)
     ENABLE_SVE_FOR_NS=1
     ENABLE_SVE_FOR_SWD=1
     ENABLE_STACK_PROTECTOR=strong
+    # Multi-core PSCI support for secondary CPU boot
+    ENABLE_MULTICORE=1
   )
 
   # Output paths depend on debug/release

boards/arm/fvp_corstone1000/board.yml

@@ -4,3 +4,5 @@ board:
   vendor: arm
   socs:
   - name: a320
+    variants:
+    - name: smp

boards/arm/fvp_corstone1000/doc/index.rst

@@ -42,9 +42,10 @@ Supported Features
 Board Variants
 ==============
 
-The following board target is available:
+The following board targets are available:
 
-* ``fvp_corstone1000/a320`` - ARMv9.2-A with Cortex-A320 CPU
+* ``fvp_corstone1000/a320`` - single-core ARMv9.2-A with Cortex-A320 CPU
+* ``fvp_corstone1000/a320/smp`` - quad-core SMP with all 4 Cortex-A320 CPUs
 
 Memory Map
 ==========

boards/arm/fvp_corstone1000/fvp_corstone1000.dtsi

@@ -9,6 +9,11 @@
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	chosen {
 		zephyr,sram = &dram0;
 		zephyr,flash = &flash0;

boards/arm/fvp_corstone1000/fvp_corstone1000_a320_smp.dts

@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2026 BayLibre SAS
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "fvp_corstone1000_a320.dts"

boards/arm/fvp_corstone1000/fvp_corstone1000_a320_smp.yaml

@@ -0,0 +1,16 @@
+# Copyright (c) 2026 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: fvp_corstone1000/a320/smp
+name: Arm Corstone-1000-A320 Fixed Virtual Platform (SMP)
+arch: arm64
+type: sim
+simulation:
+  - name: armfvp
+    exec: FVP_Corstone-1000-A320
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 128
+flash: 64
+vendor: arm

boards/arm/fvp_corstone1000/fvp_corstone1000_a320_smp_defconfig

@@ -0,0 +1,39 @@
+# Copyright (c) 2026 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# Enable Timer and Sys clock
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+CONFIG_ARM_ARCH_TIMER=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable serial port
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Run in Non-Secure mode (EL1NS) - TF-A handles secure boot
+CONFIG_ARMV8_A_NS=y
+
+# PSCI support for CPU power management
+CONFIG_PM_CPU_OPS=y
+
+# 64-bit timeout for long-running operations
+CONFIG_TIMEOUT_64BIT=y
+
+# Cache management
+CONFIG_CACHE_MANAGEMENT=y
+
+# SMP support - 4 Cortex-A320 cores
+CONFIG_SMP=y
+CONFIG_MP_MAX_NUM_CPUS=4
+CONFIG_MAX_THREAD_BYTES=3
+
+# TF-A warm boot does not set VMPIDR_EL2 for secondary CPUs.
+# Without this, EL1 reads of MPIDR_EL1 return 0 on secondary cores.
+CONFIG_ARM64_SET_VMPIDR_EL2=y

boards/arm/fvp_corstone1000/sysbuild.cmake

@@ -193,6 +193,11 @@ set(TFM_CMAKE_ARGS
   -DCORSTONE1000_DSU_120T=TRUE
 )
 
+# Multi-core support: boot all 4 host CPUs (secondaries enter holding pen)
+if("${BOARD_QUALIFIERS}" MATCHES "/smp$")
+  list(APPEND TFM_CMAKE_ARGS -DENABLE_MULTICORE=TRUE)
+endif()
+
 # Add toolchain bin directory to CMAKE_PROGRAM_PATH so CMake can find the compiler
 if(ARM_GCC_M_TOOLCHAIN_DIR)
   list(APPEND TFM_CMAKE_ARGS "-DCMAKE_PROGRAM_PATH=${ARM_GCC_M_TOOLCHAIN_DIR}")
@@ -292,6 +297,11 @@ set(TFA_EXTRA_ARGS
   NR_OF_IMAGES_IN_FW_BANK=4
 )
 
+# Multi-core PSCI support for secondary CPU boot
+if("${BOARD_QUALIFIERS}" MATCHES "/smp$")
+  list(APPEND TFA_EXTRA_ARGS ENABLE_MULTICORE=1)
+endif()
+
 # Find cross compiler for AArch64
 if(DEFINED ENV{CROSS_COMPILE})
   set(TFA_CROSS_COMPILE $ENV{CROSS_COMPILE})

zephyr/patches.yml

@@ -11,3 +11,18 @@ patches:
       Add DSU-120T PPU driver for Cortex-A320 host power-on.
       Required to boot the host CPU on the Corstone-1000-A320 FVP.
       Upstream commit: 991c6ebc381238a4189cec08a59a9b1c1407dcee
+
+  - path: 0002-fix-corstone1000-fix-secondary-core-hold-pen-cache-c.patch
+    sha256sum: 9386c86edb6f62570e0ea79ca9083a48f4c2d4670fcf7ee88da6a6538901fe9b
+    module: trusted-firmware-a
+    author: Nicolas Pitre
+    email: npitre@baylibre.com
+    date: 2026-02-12
+    upstreamable: true
+    comments: |
+      Fix secondary core hold pen cache coherency issue.
+      BL2's cache flush during BL2-to-BL31 transition pushes stale cached
+      data over the WAIT values that secondary CPUs wrote from non-cached
+      context. Fix by cache-line-aligning hold slots (64-byte stride),
+      moving hold base past FW_CONFIG area, and having pwr_domain_on
+      explicitly write all slots before flushing.