drivers: i2s: Added Apollo510 I2S driver.

I2S driver support standard format, short/long sync, left/right justified.
Supporting 2 channels as a default.

Signed-off-by: Lewis Lee <llee@ambiq.com>

Author: boostjw

boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi

@@ -272,6 +272,24 @@
 		};
 	};
 
+	i2s0_default: i2s0_default {
+		group0 {
+			pinmux = <I2S0_SDIN_P4>,
+				 <I2S0_CLK_P5>,
+				 <I2S0_SDOUT_P6>,
+				 <I2S0_WS_P7>;
+		};
+	};
+
+	i2s1_default: i2s1_default {
+		group0 {
+			pinmux = <I2S1_CLK_P16>,
+				 <I2S1_SDOUT_P17>,
+				 <I2S1_WS_P18>,
+				 <I2S1_SDIN_P19>;
+		};
+	};
+
 	mspi0_default: mspi0_default {
 		group0 {
 			pinmux = <MSPI0_0_P64>,

boards/ambiq/apollo510_evb/apollo510_evb.dts

@@ -211,6 +211,18 @@ zephyr_udc0: &usb {
 	status = "disabled";
 };
 
+&i2s0 {
+	pinctrl-0 = <&i2s0_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&i2s1 {
+	pinctrl-0 = <&i2s1_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
 &gpio0_31 {
 	status = "okay";
 };

boards/ambiq/apollo510_evb/apollo510_evb.yaml

@@ -20,6 +20,7 @@ supported:
   - clock_control
   - usbd
   - pdm
+  - i2s
   - mspi
 testing:
   ignore_tags:

drivers/i2s/CMakeLists.txt

@@ -18,3 +18,4 @@ zephyr_library_sources_ifdef(CONFIG_I2S_SILABS_SIWX91X	i2s_silabs_siwx91x.c)
 zephyr_library_sources_ifdef(CONFIG_I2S_TEST		i2s_test.c)
 zephyr_library_sources_ifdef(CONFIG_I2S_STM32_SAI   i2s_stm32_sai.c)
 zephyr_library_sources_ifdef(CONFIG_I2S_RENESAS_RA_SSIE  i2s_renesas_ra_ssie.c)
+zephyr_library_sources_ifdef(CONFIG_I2S_AMBIQ		i2s_ambiq.c)

drivers/i2s/Kconfig.ambiq

@@ -0,0 +1,37 @@
+# Copyright (c) 2025 Ambiq Micro Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config I2S_AMBIQ
+	bool "Ambiq I2S driver"
+	default y
+	depends on DT_HAS_AMBIQ_I2S_ENABLED
+	select AMBIQ_HAL
+	select AMBIQ_HAL_USE_I2S
+	select PINCTRL
+	help
+	  Enable support for Ambiq I2S driver for Apollo 5 MCU.
+
+if I2S_AMBIQ
+
+config I2S_AMBIQ_HANDLE_CACHE
+	bool "Turn on cache handling in I2S driver"
+	default y
+	depends on CACHE_MANAGEMENT && DCACHE
+	help
+	  Disable this if cache has been handled in upper layers.
+
+config I2S_AMBIQ_BUFFER_ALIGNMENT
+	int "Set the I2S DMA TCB buffer alignment"
+	default DCACHE_LINE_SIZE if DCACHE
+	help
+	  I2S buffer should be 32bytes aligned when placed in cachable region.
+
+config I2S_AMBIQ_RX_BLOCK_COUNT
+	int "RX queue length"
+	default 4
+
+config I2S_AMBIQ_TX_BLOCK_COUNT
+	int "TX queue length"
+	default 4
+
+endif # I2S_AMBIQ