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tpambornashif
tpambor
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nashif
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dts: arm: st: add reset for lptim
Add resets property to lptim binding and define resets for all lptim instances in device tree files for STM32 MCUs. Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
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16 files changed

+25
-2
lines changed

16 files changed

+25
-2
lines changed

‎dts/arm/st/g0/stm32g0.dtsi‎

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@@ -259,6 +259,7 @@
259259
lptim1: timers@40007c00 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB1, 31)>;
262+
resets = <&rctl STM32_RESET(APB1L, 31)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40007c00 0x400>;

‎dts/arm/st/g4/stm32g4.dtsi‎

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@@ -416,6 +416,7 @@
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lptim1: timers@40007c00 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB1, 31)>;
419+
resets = <&rctl STM32_RESET(APB1L, 31)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40007c00 0x400>;

‎dts/arm/st/h5/stm32h5.dtsi‎

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@@ -231,6 +231,7 @@
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lptim1: timers@44004400 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB3, 11)>;
234+
resets = <&rctl STM32_RESET(APB3, 11)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44004400 0x400>;
@@ -242,6 +243,7 @@
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lptim2: timers@40009400 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB1_2, 5)>;
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resets = <&rctl STM32_RESET(APB1H, 5)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40009400 0x400>;

‎dts/arm/st/h5/stm32h562.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -81,6 +81,7 @@
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lptim3: timers@44004800 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB3, 12)>;
84+
resets = <&rctl STM32_RESET(APB3, 12)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44004800 0x400>;
@@ -92,6 +93,7 @@
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lptim4: timers@44004c00 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB3, 13)>;
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resets = <&rctl STM32_RESET(APB3, 13)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44004c00 0x400>;
@@ -103,6 +105,7 @@
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lptim5: timers@44005000 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB3, 14)>;
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resets = <&rctl STM32_RESET(APB3, 14)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44005000 0x400>;
@@ -114,6 +117,7 @@
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lptim6: timers@44005400 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB3, 15)>;
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resets = <&rctl STM32_RESET(APB3, 15)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44005400 0x400>;

‎dts/arm/st/h7/stm32h7.dtsi‎

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@@ -932,6 +932,7 @@
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lptim1: timers@40002400 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB1, 9)>;
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resets = <&rctl STM32_RESET(APB1L, 9)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40002400 0x400>;

‎dts/arm/st/h7rs/stm32h7rs.dtsi‎

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@@ -868,6 +868,7 @@
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lptim1: timers@40002400 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB1, 9)>;
871+
resets = <&rctl STM32_RESET(APB1L, 9)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40002400 0x400>;

‎dts/arm/st/l0/stm32l0.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -311,6 +311,7 @@
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lptim1: timers@40007c00 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB1, 31)>;
314+
resets = <&rctl STM32_RESET(APB1, 31)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40007c00 0x400>;

‎dts/arm/st/l4/stm32l4.dtsi‎

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@@ -490,6 +490,7 @@
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lptim1: timers@40007c00 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB1, 31)>;
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resets = <&rctl STM32_RESET(APB1L, 31)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40007c00 0x400>;
@@ -504,6 +505,7 @@
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#size-cells = <0>;
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reg = <0x40009400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1_2, 5)>;
508+
resets = <&rctl STM32_RESET(APB1H, 5)>;
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interrupts = <66 1>;
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interrupt-names = "wakeup";
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status = "disabled";

‎dts/arm/st/l5/stm32l5.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -331,6 +331,7 @@
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lptim1: timers@40007c00 {
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compatible = "st,stm32-lptim";
333333
clocks = <&rcc STM32_CLOCK(APB1, 31)>;
334+
resets = <&rctl STM32_RESET(APB1L, 31)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40007c00 0x400>;

‎dts/arm/st/u0/stm32u0.dtsi‎

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@@ -582,6 +582,7 @@
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lptim1: timers@40007c00 {
583583
compatible = "st,stm32-lptim";
584584
clocks = <&rcc STM32_CLOCK(APB1, 31)>;
585+
resets = <&rctl STM32_RESET(APB1L, 31)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40007c00 0x400>;
@@ -593,6 +594,7 @@
593594
lptim2: timers@40009400 {
594595
compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB1, 30)>;
597+
resets = <&rctl STM32_RESET(APB1L, 30)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40009400 0x400>;

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