drivers: Implement async flash transactions for stm32's

Added optional use of the stm32 hal async flash write and erase
capabilities on the l4, f4, and h7 soc families. It is implemented
using semaphores to allow for other threads to take action during
the erase/write actions. This can be optionally enabled or disabled
using the FLASH_STM32_ASYNC config option.

Signed-off-by: Parker Owen <jpowen898@gmail.com>

Author: jpowen898

drivers/flash/Kconfig

@@ -17,6 +17,12 @@ config FLASH_HAS_EX_OP
 	  This option is selected by drivers that support flash extended
 	  operations.
 
+config FLASH_HAS_ASYNC_OPS
+	bool
+	help
+	  This option is selected by drivers that support asynchronous 
+	  flash operations.
+
 config FLASH_HAS_EXPLICIT_ERASE
 	bool
 	help

drivers/flash/Kconfig.stm32

@@ -25,6 +25,9 @@ menuconfig SOC_FLASH_STM32
 	select MPU_ALLOW_FLASH_WRITE if ARM_MPU
 	select USE_STM32_HAL_FLASH if BT_STM32WBA
 	select USE_STM32_HAL_FLASH_EX if BT_STM32WBA
+	select FLASH_HAS_ASYNC_OPS if SOC_SERIES_STM32L4X || \
+								  SOC_SERIES_STM32F4X || \
+								  SOC_SERIES_STM32H7X
 	help
 	  Enable flash driver for STM32 series
 
@@ -100,4 +103,15 @@ config USE_MICROCHIP_QSPI_FLASH_WITH_STM32
 	  the Global Block Protection Unlock instruction (ULBPR - 98H),
 	  and write with SPI_NOR_CMD_PP_1_1_4 on 4 lines
 
+config FLASH_STM32_ASYNC
+	bool "Enable asynchronous flash operations"
+	depends on CONFIG_MULTITHREADING || SOC_SERIES_STM32L4X || \
+			   SOC_SERIES_STM32F4X || SOC_SERIES_STM32H7X
+	select FLASH_HAS_ASYNC_OPS
+	select USE_STM32_HAL_FLASH
+	select USE_STM32_HAL_FLASH_EX
+	default y
+	help
+	  Enables asynchronous flash operations.
+
 endif # SOC_FLASH_STM32

drivers/flash/flash_stm32.c

@@ -416,6 +416,31 @@ static DEVICE_API(flash, flash_stm32_api) = {
 #endif
 };
 
+#if defined(CONFIG_FLASH_STM32_ASYNC)
+static struct flash_stm32_priv *flash_dev;
+
+/* IRQ handler function for async flash mode */
+void flash_stm32_irq_handler(void)
+{
+	HAL_FLASH_IRQHandler();
+	if(flash_dev->async_complete || flash_dev->async_error) {
+		k_sem_give(&flash_dev->async_sem);
+	}
+}
+
+/* cube hal functions for end of a async flash operation */
+void HAL_FLASH_EndOfOperationCallback(uint32_t op_ret_val)
+{
+	flash_dev->async_complete = true;
+	flash_dev->async_ret = op_ret_val;
+}
+void HAL_FLASH_OperationErrorCallback(uint32_t op_ret_val)
+{
+	flash_dev->async_error = true;
+	flash_dev->async_ret = op_ret_val;
+}
+#endif /* CONFIG_FLASH_STM32_ASYNC */
+
 static int stm32_flash_init(const struct device *dev)
 {
 	int rc;
@@ -457,6 +482,12 @@ static int stm32_flash_init(const struct device *dev)
 #endif /* CONFIG_SOC_SERIES_STM32WBX */
 
 	flash_stm32_sem_init(dev);
+#if defined(CONFIG_FLASH_STM32_ASYNC)
+	flash_dev = FLASH_STM32_PRIV(dev);
+	flash_stm32_async_sem_init(dev);
+	IRQ_CONNECT(FLASH_IRQn, 0, flash_stm32_irq_handler, NULL, 0);
+	irq_enable(FLASH_IRQn);
+#endif /* CONFIG_FLASH_STM32_ASYNC */
 
 	LOG_DBG("Flash @0x%x initialized. BS: %zu",
 		FLASH_STM32_BASE_ADDRESS,

drivers/flash/flash_stm32.h

@@ -29,6 +29,12 @@ struct flash_stm32_priv {
 	struct stm32_pclken pclken;
 #endif
 	struct k_sem sem;
+#if defined(CONFIG_FLASH_STM32_ASYNC)
+	struct k_sem async_sem;
+	bool async_complete;
+	bool async_error;
+	uint32_t async_ret;
+#endif /* CONFIG_FLASH_STM32_ASYNC */
 };
 
 #if DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
@@ -310,6 +316,9 @@ static inline void _flash_stm32_sem_give(const struct device *dev)
 #define flash_stm32_sem_init(dev) k_sem_init(&FLASH_STM32_PRIV(dev)->sem, 1, 1)
 #define flash_stm32_sem_take(dev) _flash_stm32_sem_take(dev)
 #define flash_stm32_sem_give(dev) _flash_stm32_sem_give(dev)
+#if defined(CONFIG_FLASH_STM32_ASYNC)
+#define flash_stm32_async_sem_init(dev) k_sem_init(&FLASH_STM32_PRIV(dev)->async_sem, 0, 1)
+#endif /* CONFIG_FLASH_STM32_ASYNC */
 #else
 #define flash_stm32_sem_init(dev)
 #define flash_stm32_sem_take(dev)

drivers/flash/flash_stm32f4x.c

@@ -28,14 +28,26 @@ typedef uint32_t flash_prg_t;
 #define FLASH_PROGRAM_SIZE FLASH_PSIZE_WORD
 #elif FLASH_STM32_WRITE_BLOCK_SIZE == 2
 typedef uint16_t flash_prg_t;
-#define FLASH_PROGRAM_SIZE FLASH_PSIZE_HALF_WORD
 #elif FLASH_STM32_WRITE_BLOCK_SIZE == 1
 typedef uint8_t flash_prg_t;
-#define FLASH_PROGRAM_SIZE FLASH_PSIZE_BYTE
 #else
 #error Write block size must be a power of 2, from 1 to 8
 #endif
 
+#if defined(CONFIG_FLASH_STM32_ASYNC)
+#if FLASH_STM32_WRITE_BLOCK_SIZE == 8
+#define FLASH_TYPEPROGRAM_SIZE FLASH_TYPEPROGRAM_DOUBLEWORD
+#elif FLASH_STM32_WRITE_BLOCK_SIZE == 4
+#define FLASH_TYPEPROGRAM_SIZE FLASH_TYPEPROGRAM_WORD
+#elif FLASH_STM32_WRITE_BLOCK_SIZE == 2
+#define FLASH_TYPEPROGRAM_SIZE FLASH_TYPEPROGRAM_HALFWORD
+#elif FLASH_STM32_WRITE_BLOCK_SIZE == 1
+#define FLASH_TYPEPROGRAM_SIZE FLASH_TYPEPROGRAM_BYTE
+#else
+#error Write block size must be a power of 2, from 1 to 8
+#endif
+#endif  /* CONFIG_FLASH_STM32_ASYNC */
+
 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
 			     uint32_t len,
 			     bool write)
@@ -82,12 +94,28 @@ static inline void flush_cache(FLASH_TypeDef *regs)
 
 static int write_value(const struct device *dev, off_t offset, flash_prg_t val)
 {
+	int rc;
+#if defined(CONFIG_FLASH_STM32_ASYNC)
+	FLASH_STM32_PRIV(dev)->async_complete = false;
+	FLASH_STM32_PRIV(dev)->async_error = false;
+	HAL_FLASH_Program_IT(FLASH_TYPEPROGRAM_SIZE, offset + FLASH_STM32_BASE_ADDRESS, val);
+	k_sem_take(&FLASH_STM32_PRIV(dev)->async_sem, K_FOREVER);
+	if (FLASH_STM32_PRIV(dev)->async_complete) {
+		LOG_DBG("Flash write successful. Wrote 0x%x at 0x%lx",
+			val, offset + FLASH_STM32_BASE_ADDRESS);
+		rc = 0;
+	} else {
+		if (FLASH_STM32_PRIV(dev)->async_error) {
+			LOG_ERR("Flash write failed %d", FLASH_STM32_PRIV(dev)->async_ret);
+		}
+		rc = -EIO;
+	}
+#else /* CONFIG_FLASH_STM32_ASYNC */
 	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
 #if defined(FLASH_OPTCR_DB1M)
 	bool dcache_enabled = false;
 #endif /* FLASH_OPTCR_DB*/
 	uint32_t tmp;
-	int rc;
 
 	/* if the control register is locked, do not fail silently */
 	if (regs->CR & FLASH_CR_LOCK) {
@@ -130,15 +158,39 @@ static int write_value(const struct device *dev, off_t offset, flash_prg_t val)
 		regs->ACR |= FLASH_ACR_DCEN;
 	}
 #endif /* FLASH_OPTCR_DB1M */
-
+#endif /* CONFIG_FLASH_STM32_ASYNC */
 	return rc;
 }
 
 static int erase_sector(const struct device *dev, uint32_t sector)
 {
+	int rc;
+#if defined(CONFIG_FLASH_STM32_ASYNC)
+	FLASH_STM32_PRIV(dev)->async_complete = false;
+	FLASH_STM32_PRIV(dev)->async_error = false;
+	FLASH_EraseInitTypeDef erase_init = {
+		.TypeErase    = FLASH_TYPEERASE_SECTORS,
+		.Banks        = 1, // dual bank flash not supported
+		.Sector       = sector,
+		.NbSectors    = 1,
+		.VoltageRange = FLASH_VOLTAGE_RANGE_4,
+
+	};
+	HAL_FLASHEx_Erase_IT(&erase_init);
+	k_sem_take(&FLASH_STM32_PRIV(dev)->async_sem, K_FOREVER);
+	if (FLASH_STM32_PRIV(dev)->async_complete) {
+		LOG_DBG("Flash erase successful. Erased sector %d at 0x%x",
+			sector, FLASH_STM32_PRIV(dev)->async_ret);
+		rc = 0;
+	} else {
+		if (FLASH_STM32_PRIV(dev)->async_error) {
+			LOG_ERR("Flash erase failed %d", FLASH_STM32_PRIV(dev)->async_ret);
+		}
+		rc = -EIO;
+	}
+#else
 	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
 	uint32_t tmp;
-	int rc;
 
 	/* if the control register is locked, do not fail silently */
 	if (regs->CR & FLASH_CR_LOCK) {
@@ -180,7 +232,7 @@ static int erase_sector(const struct device *dev, uint32_t sector)
 
 	rc = flash_stm32_wait_flash_idle(dev);
 	regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB);
-
+#endif
 	return rc;
 }
 

drivers/flash/flash_stm32h7x.c

@@ -514,7 +514,30 @@ static int erase_sector(const struct device *dev, int offset)
 {
 	int rc;
 	struct flash_stm32_sector_t sector = get_sector(dev, offset);
-
+#if defined(CONFIG_FLASH_STM32_ASYNC)
+	FLASH_STM32_PRIV(dev)->async_complete = false;
+	FLASH_STM32_PRIV(dev)->async_error = false;
+	FLASH_EraseInitTypeDef erase_init = {
+        .TypeErase    = FLASH_TYPEERASE_SECTORS,
+		.Banks        = sector.bank,
+		.Sector       = sector.sector_index,
+		.NbSectors    = 1,
+		.VoltageRange = FLASH_VOLTAGE_RANGE_4,
+
+	};
+	HAL_FLASHEx_Erase_IT(&erase_init);
+	k_sem_take(&FLASH_STM32_PRIV(dev)->async_sem, K_FOREVER);
+	if (FLASH_STM32_PRIV(dev)->async_complete) {
+		LOG_DBG("Flash erase successful. Erased %lu bytes at 0x%x",
+			FLASH_SECTOR_SIZE, FLASH_STM32_PRIV(dev)->async_ret);
+		rc = 0;
+	} else {
+		if (FLASH_STM32_PRIV(dev)->async_error) {
+			LOG_ERR("Flash erase failed %d", FLASH_STM32_PRIV(dev)->async_ret);
+		}
+		rc = -EIO;
+	}
+#else
 	if (sector.bank == 0) {
 
 		LOG_ERR("Offset %ld does not exist", (long)offset);
@@ -539,7 +562,7 @@ static int erase_sector(const struct device *dev, int offset)
 
 	rc = flash_stm32_wait_flash_idle(dev);
 	*(sector.cr) &= ~(FLASH_CR_SER | FLASH_CR_SNB);
-
+#endif
 	return rc;
 }
 
@@ -557,6 +580,7 @@ int flash_stm32_block_erase_loop(const struct device *dev, unsigned int offset,
 	return rc;
 }
 
+#if !defined(CONFIG_FLASH_STM32_ASYNC)
 static int wait_write_queue(const struct flash_stm32_sector_t *sector)
 {
 	int64_t timeout_time = k_uptime_get() + 100;
@@ -570,11 +594,33 @@ static int wait_write_queue(const struct flash_stm32_sector_t *sector)
 
 	return 0;
 }
+#endif /* !CONFIG_FLASH_STM32_ASYNC */
 
 static int write_ndwords(const struct device *dev, off_t offset, const uint64_t *data, uint8_t n)
 {
-	volatile uint64_t *flash = (uint64_t *)(offset + FLASH_STM32_BASE_ADDRESS);
 	int rc;
+#if defined(CONFIG_FLASH_STM32_ASYNC)
+	for(size_t i = 0; i < n; i += FLASH_NB_32BITWORD_IN_FLASHWORD) {
+		FLASH_STM32_PRIV(dev)->async_complete = false;
+		FLASH_STM32_PRIV(dev)->async_error = false;
+		uint32_t wordAddr = (uint32_t)&data[i];
+		HAL_FLASH_Program_IT(FLASH_TYPEPROGRAM_FLASHWORD, offset + FLASH_STM32_BASE_ADDRESS, wordAddr);
+		k_sem_take(&FLASH_STM32_PRIV(dev)->async_sem, K_FOREVER);
+		if (FLASH_STM32_PRIV(dev)->async_complete) {
+			LOG_DBG("Flash write successful. Wrote %u bytes to 0x%x",
+				FLASH_STM32_WRITE_BLOCK_SIZE, FLASH_STM32_PRIV(dev)->async_ret);
+			rc = 0;
+		}
+		else{
+			if (FLASH_STM32_PRIV(dev)->async_error) {
+				LOG_ERR("Flash write failed %d", FLASH_STM32_PRIV(dev)->async_ret);
+			}
+			rc = -EIO;
+		}
+
+	}
+#else
+	volatile uint64_t *flash = (uint64_t *)(offset + FLASH_STM32_BASE_ADDRESS);
 	int i;
 	struct flash_stm32_sector_t sector = get_sector(dev, offset);
 
@@ -623,7 +669,7 @@ static int write_ndwords(const struct device *dev, off_t offset, const uint64_t
 
 	/* Clear the PG bit */
 	*(sector.cr) &= (~FLASH_CR_PG);
-
+#endif
 	return rc;
 }
 
@@ -927,6 +973,31 @@ static DEVICE_API(flash, flash_stm32h7_api) = {
 #endif
 };
 
+#if defined(CONFIG_FLASH_STM32_ASYNC)
+static struct flash_stm32_priv *flash_dev;
+
+/* IRQ handler function for async flash mode */
+void flash_stm32_irq_handler(void)
+{
+	HAL_FLASH_IRQHandler();
+	if(flash_dev->async_complete || flash_dev->async_error) {
+		k_sem_give(&flash_dev->async_sem);
+	}
+}
+
+/* cube hal functions for end of a async flash operation */
+void HAL_FLASH_EndOfOperationCallback(uint32_t op_ret_val)
+{
+	flash_dev->async_complete = true;
+	flash_dev->async_ret = op_ret_val;
+}
+void HAL_FLASH_OperationErrorCallback(uint32_t op_ret_val)
+{
+	flash_dev->async_error = true;
+	flash_dev->async_ret = op_ret_val;
+}
+#endif /* CONFIG_FLASH_STM32_ASYNC */
+
 static int stm32h7_flash_init(const struct device *dev)
 {
 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
@@ -946,6 +1017,12 @@ static int stm32h7_flash_init(const struct device *dev)
 	}
 #endif
 	flash_stm32_sem_init(dev);
+#if defined(CONFIG_FLASH_STM32_ASYNC)
+	flash_dev = FLASH_STM32_PRIV(dev);
+	flash_stm32_async_sem_init(dev);
+	IRQ_CONNECT(FLASH_IRQn, 0, flash_stm32_irq_handler, NULL, 0);
+	irq_enable(FLASH_IRQn);
+#endif /* CONFIG_FLASH_STM32_ASYNC */
 
 	LOG_DBG("Flash initialized. BS: %zu", flash_stm32h7_parameters.write_block_size);