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include: dt-bindings: pinctrl: silabs: Doxygen clean-up
This commit cleans up the Doxygen documentation for the Silicon Labs pinctrl DT helpers by ensuring documentation is actually helpful and not just exposing hundreds of otherwise self-describing macros. Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
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‎include/zephyr/dt-bindings/pinctrl/silabs/xg21-pinctrl.h‎

Lines changed: 73 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,85 @@
11
/*
2-
* Copyright (c) 2025 Silicon Laboratories Inc.
2+
* Copyright (c) 2026 Silicon Laboratories Inc.
33
* SPDX-License-Identifier: Apache-2.0
44
*
5-
* Pin Control for Silicon Labs XG21 devices
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* Pin Control for Silicon Labs xG21 devices
66
*
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* This file was generated by the script gen_pinctrl.py in the hal_silabs module.
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* Do not manually edit.
99
*/
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/**
12+
* @file
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* @brief Devicetree pin control helpers for Silicon Labs xG21
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* @ingroup pinctrl_xg21
15+
*/
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1117
#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_
1218
#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_
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#include <zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
1521

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/**
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* @addtogroup silabs_pinctrl Silicon Labs pin control helpers
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* @ingroup devicetree-pinctrl
25+
*/
26+
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/**
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* @defgroup pinctrl_xg21 Silicon Labs xG21 pin control helpers
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* @brief Macros for pin control configuration of Silicon Labs xG21
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* @ingroup silabs_pinctrl
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*
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* The macros follow the following naming convention:
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* @c \<PERIPHERAL\>\_\<SIGNAL\>\_P\<PORT\>\_\<PIN\>.
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*
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* For example, @c USART0_TX_PC0 corresponds to the @c TX signal of @c USART0
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* mapped to routing port @c C pin @c 0.
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*
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* @code{.dts}
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* #include <zephyr/dt-bindings/pinctrl/silabs/xg21-pinctrl.h>
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*
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* &pinctrl {
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* usart0_default: usart0_default {
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* group0 {
44+
* pins = <USART0_TX_PC0>, <USART0_CLK_PC2>;
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* drive-push-pull;
46+
* output-high;
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* };
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* group1 {
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* pins = <USART0_RX_PC1>;
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* input-enable;
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* };
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* };
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* };
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* @endcode
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*
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* Valid peripherals and signals are:
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*
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* - @c ACMP0: @c ACMPOUT
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* - @c ACMP1: @c ACMPOUT
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* - @c CMU: @c CLKIN0, @c CLKOUT0, @c CLKOUT1, @c CLKOUT2
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* - @c GPIO: @c SWCLKTCK, @c SWDIOTMS, @c SWV, @c TDI, @c TDO, @c TRACECLK, @c TRACEDATA0
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* - @c I2C0: @c SCL, @c SDA
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* - @c I2C1: @c SCL, @c SDA
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* - @c LETIMER0: @c OUT0, @c OUT1
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* - @c MODEM: @c ANT0, @c ANT1, @c DCLK, @c DIN, @c DOUT
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* - @c PRS0: @c ASYNCH0, @c ASYNCH1, @c ASYNCH10, @c ASYNCH11, @c ASYNCH2, @c ASYNCH3, @c ASYNCH4,
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* @c ASYNCH5, @c ASYNCH6, @c ASYNCH7, @c ASYNCH8, @c ASYNCH9, @c SYNCH0, @c SYNCH1, @c SYNCH2, @c
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* SYNCH3
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* - @c PTI: @c DCLK, @c DFRAME, @c DOUT
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* - @c TIMER0: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
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* - @c TIMER1: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
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* - @c TIMER2: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
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* - @c TIMER3: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
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* - @c USART0: @c CLK, @c CS, @c CTS, @c RTS, @c RX, @c TX
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* - @c USART1: @c CLK, @c CS, @c CTS, @c RTS, @c RX, @c TX
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* - @c USART2: @c CLK, @c CS, @c CTS, @c RTS, @c RX, @c TX
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*
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* @{
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*/
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/** @cond INTERNAL_HIDDEN */
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#define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
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#define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
@@ -1230,4 +1297,8 @@
12301297
#define ABUS_CDODD1_ACMP0 SILABS_ABUS(0x2, 0x3, 0x2)
12311298
#define ABUS_CDODD1_ACMP1 SILABS_ABUS(0x2, 0x3, 0x3)
12321299

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/** @endcond */
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/** @} */
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12331304
#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_ */

‎include/zephyr/dt-bindings/pinctrl/silabs/xg22-pinctrl.h‎

Lines changed: 75 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,87 @@
11
/*
2-
* Copyright (c) 2025 Silicon Laboratories Inc.
2+
* Copyright (c) 2026 Silicon Laboratories Inc.
33
* SPDX-License-Identifier: Apache-2.0
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*
5-
* Pin Control for Silicon Labs XG22 devices
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* Pin Control for Silicon Labs xG22 devices
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*
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* This file was generated by the script gen_pinctrl.py in the hal_silabs module.
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* Do not manually edit.
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*/
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/**
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* @file
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* @brief Devicetree pin control helpers for Silicon Labs xG22
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* @ingroup pinctrl_xg22
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*/
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1117
#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG22_PINCTRL_H_
1218
#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG22_PINCTRL_H_
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#include <zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
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/**
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* @addtogroup silabs_pinctrl Silicon Labs pin control helpers
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* @ingroup devicetree-pinctrl
25+
*/
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/**
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* @defgroup pinctrl_xg22 Silicon Labs xG22 pin control helpers
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* @brief Macros for pin control configuration of Silicon Labs xG22
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* @ingroup silabs_pinctrl
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*
32+
* The macros follow the following naming convention:
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* @c \<PERIPHERAL\>\_\<SIGNAL\>\_P\<PORT\>\_\<PIN\>.
34+
*
35+
* For example, @c USART0_TX_PC0 corresponds to the @c TX signal of @c USART0
36+
* mapped to routing port @c C pin @c 0.
37+
*
38+
* @code{.dts}
39+
* #include <zephyr/dt-bindings/pinctrl/silabs/xg22-pinctrl.h>
40+
*
41+
* &pinctrl {
42+
* usart0_default: usart0_default {
43+
* group0 {
44+
* pins = <USART0_TX_PC0>, <USART0_CLK_PC2>;
45+
* drive-push-pull;
46+
* output-high;
47+
* };
48+
* group1 {
49+
* pins = <USART0_RX_PC1>;
50+
* input-enable;
51+
* };
52+
* };
53+
* };
54+
* @endcode
55+
*
56+
* Valid peripherals and signals are:
57+
*
58+
* - @c CMU: @c CLKIN0, @c CLKOUT0, @c CLKOUT1, @c CLKOUT2
59+
* - @c DCDC: @c DCDCCOREHIDDEN
60+
* - @c EUART0: @c CTS, @c RTS, @c RX, @c TX
61+
* - @c GPIO: @c SWCLKTCK, @c SWDIOTMS, @c SWV, @c TDI, @c TDO, @c TRACECLK, @c TRACEDATA0
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* - @c I2C0: @c SCL, @c SDA
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* - @c I2C1: @c SCL, @c SDA
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* - @c LETIMER0: @c OUT0, @c OUT1
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* - @c MODEM: @c ANT0, @c ANT1, @c ANTROLLOVER, @c ANTRR0, @c ANTRR1, @c ANTRR2, @c ANTRR3, @c
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* ANTRR4, @c ANTRR5, @c ANTSWEN, @c ANTSWUS, @c ANTTRIG, @c ANTTRIGSTOP, @c DCLK, @c DIN, @c DOUT
67+
* - @c PDM: @c CLK, @c DAT0, @c DAT1
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* - @c PRS0: @c ASYNCH0, @c ASYNCH1, @c ASYNCH10, @c ASYNCH11, @c ASYNCH2, @c ASYNCH3, @c ASYNCH4,
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* @c ASYNCH5, @c ASYNCH6, @c ASYNCH7, @c ASYNCH8, @c ASYNCH9, @c SYNCH0, @c SYNCH1, @c SYNCH2, @c
70+
* SYNCH3
71+
* - @c PTI: @c DCLK, @c DFRAME, @c DOUT
72+
* - @c TIMER0: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
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* - @c TIMER1: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
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* - @c TIMER2: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
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* - @c TIMER3: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
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* - @c TIMER4: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
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* - @c USART0: @c CLK, @c CS, @c CTS, @c RTS, @c RX, @c TX
78+
* - @c USART1: @c CLK, @c CS, @c CTS, @c RTS, @c RX, @c TX
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*
80+
* @{
81+
*/
82+
83+
/** @cond INTERNAL_HIDDEN */
84+
1685
#define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 2)
1786
#define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 4, 1, 1, 3)
1887
#define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 4, 1, 2, 4)
@@ -1810,4 +1879,8 @@
18101879
#define ABUS_CDODD0_IADC0 SILABS_ABUS(0x2, 0x2, 0x1)
18111880
#define ABUS_CDODD1_IADC0 SILABS_ABUS(0x2, 0x3, 0x1)
18121881

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/** @endcond */
1883+
1884+
/** @} */
1885+
18131886
#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG22_PINCTRL_H_ */

‎include/zephyr/dt-bindings/pinctrl/silabs/xg23-pinctrl.h‎

Lines changed: 83 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,95 @@
11
/*
2-
* Copyright (c) 2025 Silicon Laboratories Inc.
2+
* Copyright (c) 2026 Silicon Laboratories Inc.
33
* SPDX-License-Identifier: Apache-2.0
44
*
5-
* Pin Control for Silicon Labs XG23 devices
5+
* Pin Control for Silicon Labs xG23 devices
66
*
77
* This file was generated by the script gen_pinctrl.py in the hal_silabs module.
88
* Do not manually edit.
99
*/
1010

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/**
12+
* @file
13+
* @brief Devicetree pin control helpers for Silicon Labs xG23
14+
* @ingroup pinctrl_xg23
15+
*/
16+
1117
#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG23_PINCTRL_H_
1218
#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG23_PINCTRL_H_
1319

1420
#include <zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
1521

22+
/**
23+
* @addtogroup silabs_pinctrl Silicon Labs pin control helpers
24+
* @ingroup devicetree-pinctrl
25+
*/
26+
27+
/**
28+
* @defgroup pinctrl_xg23 Silicon Labs xG23 pin control helpers
29+
* @brief Macros for pin control configuration of Silicon Labs xG23
30+
* @ingroup silabs_pinctrl
31+
*
32+
* The macros follow the following naming convention:
33+
* @c \<PERIPHERAL\>\_\<SIGNAL\>\_P\<PORT\>\_\<PIN\>.
34+
*
35+
* For example, @c USART0_TX_PC0 corresponds to the @c TX signal of @c USART0
36+
* mapped to routing port @c C pin @c 0.
37+
*
38+
* @code{.dts}
39+
* #include <zephyr/dt-bindings/pinctrl/silabs/xg23-pinctrl.h>
40+
*
41+
* &pinctrl {
42+
* usart0_default: usart0_default {
43+
* group0 {
44+
* pins = <USART0_TX_PC0>, <USART0_CLK_PC2>;
45+
* drive-push-pull;
46+
* output-high;
47+
* };
48+
* group1 {
49+
* pins = <USART0_RX_PC1>;
50+
* input-enable;
51+
* };
52+
* };
53+
* };
54+
* @endcode
55+
*
56+
* Valid peripherals and signals are:
57+
*
58+
* - @c ACMP0: @c ACMPOUT
59+
* - @c ACMP1: @c ACMPOUT
60+
* - @c CMU: @c CLKIN0, @c CLKOUT0, @c CLKOUT1, @c CLKOUT2
61+
* - @c EUSART0: @c CS, @c CTS, @c RTS, @c RX, @c SCLK, @c TX
62+
* - @c EUSART1: @c CS, @c CTS, @c RTS, @c RX, @c SCLK, @c TX
63+
* - @c EUSART2: @c CS, @c CTS, @c RTS, @c RX, @c SCLK, @c TX
64+
* - @c GPIO: @c SWCLKTCK, @c SWDIOTMS, @c SWV, @c TDI, @c TDO, @c TRACECLK, @c TRACEDATA0, @c
65+
* TRACEDATA1, @c TRACEDATA2, @c TRACEDATA3
66+
* - @c HFXO0: @c BUFOUTREQINASYNC
67+
* - @c I2C0: @c SCL, @c SDA
68+
* - @c I2C1: @c SCL, @c SDA
69+
* - @c KEYSCAN: @c COLOUT0, @c COLOUT1, @c COLOUT2, @c COLOUT3, @c COLOUT4, @c COLOUT5, @c COLOUT6,
70+
* @c COLOUT7, @c ROWSENSE0, @c ROWSENSE1, @c ROWSENSE2, @c ROWSENSE3, @c ROWSENSE4, @c ROWSENSE5
71+
* - @c LESENSE: @c CH0OUT, @c CH10OUT, @c CH11OUT, @c CH12OUT, @c CH13OUT, @c CH14OUT, @c CH15OUT,
72+
* @c CH1OUT, @c CH2OUT, @c CH3OUT, @c CH4OUT, @c CH5OUT, @c CH6OUT, @c CH7OUT, @c CH8OUT, @c CH9OUT
73+
* - @c LETIMER0: @c OUT0, @c OUT1
74+
* - @c MODEM: @c ANT0, @c ANT1, @c ANTROLLOVER, @c ANTRR0, @c ANTRR1, @c ANTRR2, @c ANTRR3, @c
75+
* ANTRR4, @c ANTRR5, @c ANTSWEN, @c ANTSWUS, @c ANTTRIG, @c ANTTRIGSTOP, @c DCLK, @c DIN, @c DOUT
76+
* - @c PCNT0: @c S0IN, @c S1IN
77+
* - @c PRS0: @c ASYNCH0, @c ASYNCH1, @c ASYNCH10, @c ASYNCH11, @c ASYNCH2, @c ASYNCH3, @c ASYNCH4,
78+
* @c ASYNCH5, @c ASYNCH6, @c ASYNCH7, @c ASYNCH8, @c ASYNCH9, @c SYNCH0, @c SYNCH1, @c SYNCH2, @c
79+
* SYNCH3
80+
* - @c PTI: @c DCLK, @c DFRAME, @c DOUT
81+
* - @c TIMER0: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
82+
* - @c TIMER1: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
83+
* - @c TIMER2: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
84+
* - @c TIMER3: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
85+
* - @c TIMER4: @c CC0, @c CC1, @c CC2, @c CDTI0, @c CDTI1, @c CDTI2
86+
* - @c USART0: @c CLK, @c CS, @c CTS, @c RTS, @c RX, @c TX
87+
*
88+
* @{
89+
*/
90+
91+
/** @cond INTERNAL_HIDDEN */
92+
1693
#define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 16, 1, 0, 1)
1794

1895
#define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
@@ -3261,4 +3338,8 @@
32613338
#define ABUS_CDODD1_ACMP1 SILABS_ABUS(0x2, 0x3, 0x3)
32623339
#define ABUS_CDODD1_VDAC0CH1 SILABS_ABUS(0x2, 0x3, 0x4)
32633340

3341+
/** @endcond */
3342+
3343+
/** @} */
3344+
32643345
#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG23_PINCTRL_H_ */

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