ENET RMII clock initialisation happening after PHY init on i.MX RT1062

[grumpyengineer]

Hi all, I'm moving a custom board based in an i.MX RT1062 from MBed to Zephyr and I'm having some teething trouble. I'm a lot deeper into the Zephyr workings than I anticipated.

I'm putting this in discussions as I'm not sure this is a bug.

The board has a Renesas ICS1894 RMII 10/100 PHY at address 1. Its pretty basic. No dedicated hardware reset, no interrupt.

For MBed I borrowed the stock fsl_phy.c and removed references to registers that didn't exist. All good.

For Zephyr it looks like the basic phy_mii.c driver will work:

&enet_mac {
	status = "okay";
	pinctrl-0 = <&pinmux_enet>;
	pinctrl-names = "default";
	nxp,unique-mac;
	phy-connection-type = "rmii";
	phy-handle = <&phy>;
};

&enet_mdio {
	status = "okay";
	pinctrl-0 = <&pinmux_enet_mdio>;
	pinctrl-names = "default";

	phy: phy@1 {
		status = "okay";
		compatible = "ethernet-phy";
		reg = <1>;
	};
};

Starting Zephyr I get 'Failed to reset PHY (1)' as the PHY never responds over the MDIO.

The issue appears to be that at the time of PHY init there is no 50MHz clock to the PHY. I can see the MDIO clock and data but the PHY never responds.

In MBed the first thing it does during the PHY init is enable the ENET clocks. Confirmed with a scope, the 50MHz starts and then comms on the MDIO.

If I manually change the init priorities by setting 'CONFIG_ETH_INIT_PRIORITY=50' I get PHY comms but I get build errors and although the DHCP client says it is sending discover packets nothing is actually being sent.

The only direct reference to the ENET clock I can see in the NXP hal is in ENET_Init but I don't think this is ever called. Only ENET_Up (which is also called from ENET_Init) seems to get called from Zephyr. Even so this would be called after the MDIO and PHY init.

Can someone with more than a weeks experience with Zephyr point me in the right direction?

[DerekSnell]

Hi @grumpyengineer ,

Bringing up new boards in Zephyr can be challenging. I recommend getting a board already supported in Zephyr and using it as a reference. For your RT1062, the best board to reference is the MIMXRT1060-EVK.

I used that EVK with the latest Zephyr release v4.3.0, and I found the 50 MHz RMII clock is enabled in the SOC before any device drivers initialize. It's enabled in clock_init() in soc.c, called very early in the startup code by soc_early_init_hook(). The clock output is enabled by CLOCK_InitEnetPll(&ethPllConfig), which requires CONFIG_INIT_ENET_PLL=y. The register bit to enable the clock output is set with ethPllConfig.enableClkOutput. And this output bit is enabled if the enet or enet2 device node is enabled.

I would check that startup code and see why it is not enabling the output clock on your hardware. Best regards

[grumpyengineer]

Thanks for the pointers. I've got CONFIG_INIT_ENET_PLL set to y. My big problem at the moment is not getting enough time to get properly deep into debugging before someone comes and disturbs me.