k_thread_runtime_stats: peak_cycles rises by ~1–2% across idle boundary on Cortex-M; is 1% tolerance too strict?

[minyuan-xue]

Hi,

On an ARM Cortex-M board (240 MHz, 10 kHz system tick), running zephyr/tests/kernel/usage/thread_runtime_stats/src/ test_thread_runtime_stats.c, we see peak_cycles occasionally increase by ~6k cycles (≈1–2%) between sample 3 (pre-idle) and 4 (post-idle), causing the assertion with IDLE_EVENT_STATS_PRECISION=1 to fail.

ZTEST(usage_api, test_all_stats_usage)
{
    k_tid_t tid;
    int prio = k_thread_priority_get(_current);

    tid = k_thread_create(&helper_thread, helper_stack,
                          K_THREAD_STACK_SIZEOF(helper_stack),
                          helper1, NULL, NULL, NULL,
                          prio + 2, 0, K_NO_WAIT);

    k_thread_runtime_stats_all_get(&stats1);

    busy_loop(2);   // busy 2 ticks
    k_thread_runtime_stats_all_get(&stats2);

    k_sleep(K_TICKS(2));  // helper runs 2 ticks
    k_thread_runtime_stats_all_get(&stats3);

    k_thread_abort(tid);

    k_sleep(K_TICKS(2));  // intended idle window
    k_thread_runtime_stats_all_get(&stats4);

	/*
	 * Now process the statistics after the idle event.
	 *
	 * 1. [execution_cycles] continues to increase
	 * 2. [total_cycles] increases
	 * 3. [current_cycles] had a reset event but still increases
	 * 4. [peak_cycles] does not change
	 * 5. [average_cycles] increases
	 * 6. [idle_cycles] increased once.
	 */
	zassert_true(TEST_WITHIN_X_PERCENT(stats4.peak_cycles,
					   stats3.peak_cycles, IDLE_EVENT_STATS_PRECISION), NULL);
}

A sample log (cycles):

stats3: exec=485763, total=485763, idle=0, cur=485763, peak=485763
stats4: exec=554542, total=493037, idle=61505, cur=798, peak=492239

(stats4.peak - stats3.peak )/stats3.peak ~ 1.3%， which over IDLE_EVENT_STATS_PRECISION=1%

Our understanding:
The increase comes from the non-idle “tail” before actually entering idle (abort/cleanup, sleep enqueue, scheduling/context switch, and possibly an ISR before WFI).

Questions:
Is it realistic to keep peak strictly unchanged with only 1% tolerance on all Cortex-M boards?
Should we relax the tolerance (e.g., 2–3% for ARM, like 3% for QEMU and 7% for RISC-V)?
Or any test suggestions?

Thanks!