SystemVerilog (Computer hardware description language)
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System Verilog (Computer hardware description language)
Verilog, System (Computer hardware description language)
Broader Terms
Closely Matching Concepts from Other Schemes
Sources
found: Work cat.: Spear, C. SystemVerilog for verification, c2012.
found: SystemVerilog.org home page, July 11, 2012(IEEE 1800 SystemVerilog is the industry's first unified hardware description and verification language (HDVL) standard. SystemVerilog is a major extension of the established IEEE 1364 Verilog language. It was developed originally by Accellera to dramatically improve productivity in the design of large gate-count, IP-based, bus-intensive chips. SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow. SystemVerilog has been adopted by 100's of semiconductor design companies and supported by more than 75 EDA, IP and training solutions worldwide)
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Change Notes
2012-07-13: new
2012-10-10: revised
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