From: "Ahmed S. Darwish" <darwi@linutronix.de>
To: Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
Ingo Molnar <mingo@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Andrew Cooper <andrew.cooper3@citrix.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Sean Christopherson <seanjc@google.com>,
David Woodhouse <dwmw2@infradead.org>,
Peter Zijlstra <peterz@infradead.org>,
Christian Ludloff <ludloff@gmail.com>,
Sohil Mehta <sohil.mehta@intel.com>,
John Ogness <john.ogness@linutronix.de>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>,
"Ahmed S. Darwish" <darwi@linutronix.de>
Subject: [PATCH v6 00/90] x86: Introduce a centralized CPUID data model
Date: Fri, 27 Mar 2026 03:15:14 +0100 [thread overview]
Message-ID: <20260327021645.555257-1-darwi@linutronix.de> (raw)
Hi,
Introduce a centralized x86 CPUID model, tables, and API.
Rationale for this work can be found at:
https://lore.kernel.org/lkml/874ixernra.ffs@tglx
https://gitlab.com/x86-cpuid.org/x86-cpuid-db
By the end of this series, route all X86_FEATURE queries to the CPUID
tables and fully remove x86_capability[].
The introduced tables and APIs then become a "single source of truth" for
all x86 feature state, both the hardware-backed and the Linux-synthetic.
The series is divided as follows:
# Generic updates and fixes
1 ASoC: Intel: avs: Check maximum valid CPUID leaf
2 ASoC: Intel: avs: Include CPUID header at file scope
3 tools/x86/kcpuid: Update bitfields to x86-cpuid-db v3.0
# Header disentanglement (<asm/processor.h> <=> <asm/cpuid/api.h>)
4 treewide: Explicitly include the x86 CPUID headers
5 x86/cpu: <asm/processor.h>: Do not include the CPUID API header
6 x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs
7 x86/cpuid: Introduce <asm/cpuid/leaf_types.h>
# CPUID Model (v6)
8 x86: Introduce a centralized CPUID data model
9 x86/cpuid: Introduce a centralized CPUID parser
10 x86/cpu: Rescan CPUID table after disabling PSN
11 x86/cpu: centaur/zhaoxin: Rescan CPUID(0xc0000001) after MSR writes
12 x86/cpu/transmeta: Rescan CPUID(0x1) after capability unhide
13 x86/cpu/intel: Rescan CPUID table after leaf unlock
# CPUID(0x0), CPUID(0x1), CPUID(0x80000000), CPUID(0x8000000[234])
14 x86/cpu: Use parsed CPUID(0x0)
15 x86/lib: Add CPUID(0x1) family and model calculation
16 x86/cpu: Use parsed CPUID(0x1)
17 x86/cpuid: Parse CPUID(0x80000000)
18 x86/cpu: Use parsed CPUID(0x80000000)
19 x86/cpuid: Parse CPUID(0x80000002) to CPUID(0x80000004)
20 x86/cpu: Use parsed CPUID(0x80000002) to CPUID(0x80000004)
# CPUID Model: x86 vendor discernment + debugfs support
21 x86/cpuid: Split parser tables and add vendor-qualified parsing
22 x86/cpuid: Introduce a parser debugfs interface
# CPUID(0x16), Transmeta CPUID(0x8086000[0123456]), Centaur CPUID(0xc000000[01])
23 x86/cpuid: Parse CPUID(0x16)
24 x86/tsc: Use parsed CPUID(0x16)
25 x86/cpuid: Parse Transmeta and Centaur extended ranges
26 x86/cpu: transmeta: Use parsed CPUID(0x80860000)->CPUID(0x80860006)
27 x86/cpu: transmeta: Refactor CPU information printing
28 x86/cpu: centaur: Use parsed CPUID(0xc0000001)
29 x86/cpu: zhaoxin: Use parsed CPUID(0xc0000001)
# Intel cache descriptors; CPUID(0x2)
30 x86/cpuid: Parse CPUID(0x2)
31 x86/cpuid: Warn once on invalid CPUID(0x2) iteration count
32 x86/cpuid: Introduce parsed CPUID(0x2) API
33 x86/cpu: Use parsed CPUID(0x2)
34 x86/cacheinfo: Use parsed CPUID(0x2)
35 x86/cpuid: Remove direct CPUID(0x2) query helpers
# Intel/AMD deterministic cache; CPUID(0x4), CPUID(0x8000001d)
36 x86/cpuid: Parse deterministic cache parameters CPUID leaves
37 x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code
38 x86/cacheinfo: Use parsed CPUID(0x4)
39 x86/cacheinfo: Use parsed CPUID(0x8000001d)
# Cache/TLB/mm info; CPUID(0x8000000[568])
40 x86/cpuid: Parse CPUID(0x80000005), CPUID(0x80000006), CPUID(0x80000008)
41 x86/cacheinfo: Use auto-generated data types
42 x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006)
43 x86/cacheinfo: Use parsed CPUID(0x80000006)
44 x86/cpu: Use parsed CPUID(0x80000005) and CPUID(0x80000006)
45 x86/cpu/amd: Use parsed CPUID(0x80000005)
46 x86/cpu/amd: Refactor TLB detection code
47 x86/cpu/amd: Use parsed CPUID(CPUID(0x80000005) and CPUID(0x80000006)
48 x86/cpu/hygon: Use parsed CPUID(0x80000005) and CPUID(0x80000006)
49 x86/cpu/centaur: Use parsed CPUID(0x80000005)
50 x86/cpu: Use parsed CPUID(0x80000008)
# PerfMon; CPUID(0xa), CPUID(0x1c), CPUID(0x23), CPUID(0x80000022)
51 x86/cpuid: Parse CPUID(0xa) and CPUID(0x1c)
52 x86/cpu/intel: Use parsed CPUID(0xa)
53 x86/cpu/centaur: Use parsed CPUID(0xa)
54 x86/cpu/zhaoxin: Use parsed CPUID(0xa)
55 perf/x86/intel: Use parsed CPUID(0xa)
56 perf/x86/zhaoxin: Use parsed CPUID(0xa)
57 x86/xen: Use parsed CPUID(0xa)
58 KVM: x86: Use standard CPUID(0xa) types
59 KVM: x86/pmu: Use standard CPUID(0xa) types
60 perf/x86: Remove custom CPUID(0xa) types
61 perf/x86/lbr: Use parsed CPUID(0x1c)
62 perf/x86/lbr: Remove custom CPUID(0x1c) types
63 x86/cpuid: Parse CPUID(0x23)
64 perf/x86/intel: Use parsed per-CPU CPUID(0x23)
65 perf/x86/intel: Remove custom CPUID(0x23) types
66 x86/cpuid: Parse CPUID(0x80000022)
67 perf/x86/amd/lbr: Use parsed CPUID(0x80000022)
68 perf/x86/amd: Use parsed CPUID(0x80000022)
69 KVM: x86: Use standard CPUID(0x80000022) types
70 perf/x86: Remove custom CPUID(0x80000022) types
# Power management flags; CPUID(0x80000007).EBX
71 x86/cpuid: Parse CPUID(0x80000007)
72 x86/cpu: Use parsed CPUID(0x80000007)
73 x86/cpu: amd/hygon: Use parsed CPUID(0x80000007)
74 x86/cpu: cpuinfo: Use parsed CPUID(0x80000007)
75 KVM: x86: Use parsed CPUID(0x80000007)
# Model: X86_FEATURE routing to the CPUID tables
76 x86/microcode: Allocate cpuinfo_x86 snapshots on the heap
77 x86/cpuid: Parse leaves backing X86_FEATURE words
78 x86/cpuid: Parse Linux synthetic CPUID leaves
79 x86/cpuid: Introduce a compile-time X86_FEATURE word map
80 x86/cpuid: Introduce X86_FEATURE and CPUID word APIs
81 x86/percpu: Add offset argument to x86_this_cpu_test_bit()
82 x86/cpufeature: Factor out a __static_cpu_has() helper
83 x86/asm/32: Cache CPUID(0x1).EDX in cpuid_table
84 x86: Route all feature queries to the CPUID tables
# x86_capability[] removal
85 x86/cpu: Remove x86_capability[] and x86_power initialization
86 x86/cpu/transmeta: Remove x86_capability[] CPUID initialization
87 x86/cpu: centaur/zhaoxin: Remove x86_capability[] initialization
88 KVM: x86: Remove BUILD_BUG_ON() x86_capability[] check
89 x86/cpu: Remove x86_capability[] and x86_power
# Finally
90 MAINTAINERS: Extend x86 CPUID DATABASE file coverage
Changelog v6
============
This iteration adds the following:
(I.) X86_FEATURE integration
----------------------------
The X86_FEATURE words at <asm/cpufeatures.h> are of two kinds:
(a.) Hardware-defined feature words, mirroring one CPUID output register
(b.) Linux-defined x86 feature words
For the hardware-backed words, the CPUID tables and x86_capability[] fully
overlap. Route those X86_FEATURE words to the CPUID tables instead.
For the Linux-synthetic feature words, only x86_capability[] defines them
as they have no hardware backing. Unify their handling by defining them in
x86-cpuid-db as a synthetic CPUID leaf:
<leaf id="0x4c780001">
<desc>Linux-defined synthetic feature flags</desc>
<text>
This is a Linux-defined synthetic CPUID leaf, where "Linux" is a
virtual vendor mirroring hardware vendors like AMD and Intel. The leaf
ID prefix 0x4c78 is for Linux, in its shorthand ASCII form "Lx".
The bit listing mirrors what Linux defines in its synthetic X86_FEATURE
words. The listed feature bits are expected to be stable, and
allocated new bits must be filled in that order: subleaf 0 (EAX->EDX),
subleaf 1 (EAX->EDX), and so on.
</text>
<vendors>
<vendor>Linux</vendor>
</vendors>
<subleaf id="0">
<eax>
<desc>X86_FEATURE word 3: Miscellaneous flags</desc>
<!-- .. bitfields .. -->
</eax>
<ebx>
<desc>X86_FEATURE word 7: Auxiliary flags</desc>
<!-- .. bitfields .. -->
</ebx>
<ecx>
<desc>X86_FEATURE word 8: Virtualization flags</desc>
<!-- .. bitfields .. -->
</ecx>
<!-- and so on -->
</subleaf>
</leaf>
Cover all the synthetic feature and bug words by defining CPUID(0x4c780001)
subleaf 0, CPUID(0x4c780001) subleaf 1, and CPUID(0x4c780002) for the CPU
bugs words, X86_BUG.
(II.) Preserve optimized X86_FEATURE query paths
------------------------------------------------
Feature querying is one of the hottest code paths in the x86 subsystem.
This is evident from the bitops usage and the post-boot ALTERNATIVE_TERNARY
opcode patching at <asm/cpufeature.h>.
Preserve that fast path by implementing a pure compile-time mapping from an
X86_FEATURE word to a CPUID table entry in <asm/cpuid/types.h>:
#define CPUID_FEATURE_WORDS_MAP { \
/* X86_FEATURE word, Leaf, Subleaf, Output reg */ \
__cpu_feature_word(0, 0x1, 0, CPUID_EDX), \
__cpu_feature_word(1, 0x80000001, 0, CPUID_EDX), \
__cpu_feature_word(2, 0x80860001, 0, CPUID_EDX), \
__cpu_feature_word(3, 0x4c780001, 0, CPUID_EAX), \
__cpu_feature_word(4, 0x1, 0, CPUID_ECX), \
__cpu_feature_word(5, 0xc0000001, 0, CPUID_EDX), \
__cpu_feature_word(6, 0x80000001, 0, CPUID_ECX), \
__cpu_feature_word(7, 0x4c780001, 0, CPUID_EBX), \
... \
}
Ensure that all mapped X86_FEATURE words remain "unsigned long" aligned so
that bitops access continues to work. Translate an X86_FEATURE query, at
compile time, to a bitops-ready bitmap plus bit offset.
The synthetic x86-cpuid-db CPUID leaves (0x4c78 range), remove any need to
distinguish between synthetic and hardware-backed X86_FEATURE words.
Across this whole series, treat both classes identically.
(III.) Partial CPUID Table refresh APIs
---------------------------------------
The CPUID tables now host all the X86_FEATURE words, so /never/ repopulate
those tables wholesale. Doing so would corrupt the kernel maintained state
of set and cleared feature bits, for both hardware-backed and synthetic
words. This is especially true since once all direct CPUID queries are
forbidden from the kernel, the kernel will gain even more freedom to modify
the hardware-backed feature bits at will.
But... there are areas in the kernel where parts of the table need to be
refreshed. This can happen after MSR writes, where CPUID leaves can appear
or disapper, or individual feature bits within them can get set or cleared.
To handle that, introduce the partial CPUID table refresh APIs:
void cpuid_refresh_leaf(struct cpuinfo_x86 *c, u32 leaf);
void cpuid_refresh_range(struct cpuinfo_x86 *c, u32 start, u32 end);
The CPUID tables are not a normal array, but a compile-time collection of
different types. Nonetheless, a reliable implementation was found to
bridge the compile-time layout and the run-time partial refresh logic.
(IV.) Convert more CPUID leaves
-------------------------------
Convert many more call sites to the new CPUID APIs, in the ongoing quest to
forbid the CPUID instruction in all kernel code outside the CPUID parser.
Parse the CPUID leaves required for hardware-backed X86_FEATURE words:
CPUID(0x6)
CPUID(0x7).0
CPUID(0x7).1
CPUID(0xd).1
CPUID(0x80000001)
CPUID(0x80000007)
CPUID(0x80000008)
CPUID(0x8000000a)
CPUID(0x8000001f)
CPUID(0x80000021)
Parse all Transmeta and Centaur/Zhaoxin leaves, and convert their call
sites:
CPUID(0x80860000)
CPUID(0x80860001)
CPUID(0x80860002)
CPUID(0x80860003)
CPUID(0x80860004)
CPUID(0x80860005)
CPUID(0x80860006)
CPUID(0xc0000000)
CPUID(0xc0000001)
Parse and convert the call sites for the performance monitoring
(PerfMon) leaves:
CPUID(0xa)
CPUID(0x1c)
CPUID(0x23)
CPUID(0x80000022)
Remove the custom CPUID output types from perf's <asm/perf_event.h> and
use the auto generated x86-cpuid-db output types instead.
Complete all call-site conversions for:
CPUID(0x80000005)
CPUID(0x80000006)
CPUID(0x80000008)
Previous iterations converted only the cacheinfo.c logic. This iteration
also converts cpu/common.c, cpu/centaur.c, and cpu/zhaoxin.c.
(V.) Handle Boris' review remarks
---------------------------------
Get rid of the "static vs. dynamic" CPUID leaf distinction, since that
terminology does not exist in the hardware manuals. What was previously
called a dynamic leaf is now described simply as a leaf with a subleaf
range. Adjust the CPUID API function names and update all their
kernel-doc.
Reduce commit log verbosity where appropriate. In general, keep detailed
kernel-doc only for the exported call-site APIs.
Shorten function names for the CPUID parser call-site APIs; e.g.
cpuid_parse_cpu(), cpuid_refresh_leaf(), etc.
(VI.) State of affairs
----------------------
Besides the X86_FEATURE query routing, 36 CPUID leaves are now converted
to the CPUID API. Namely:
CPUID(0x0)
CPUID(0x1)
CPUID(0x2)
CPUID(0x4)
CPUID(0x6)
CPUID(0x7)
CPUID(0x7).1
CPUID(0xa)
CPUID(0xd).1
CPUID(0x16)
CPUID(0x1c)
CPUID(0x23)
CPUID(0x23).1
CPUID(0x23).2
CPUID(0x80000000)
CPUID(0x80000001)
CPUID(0x80000002)
CPUID(0x80000003)
CPUID(0x80000004)
CPUID(0x80000005)
CPUID(0x80000006)
CPUID(0x80000007)
CPUID(0x80000008)
CPUID(0x8000000a)
CPUID(0x8000001d)
CPUID(0x8000001f)
CPUID(0x80000021)
CPUID(0x80000022)
CPUID(0x80860000)
CPUID(0x80860001)
CPUID(0x80860002)
CPUID(0x80860003)
CPUID(0x80860004)
CPUID(0x80860005)
CPUID(0x80860006)
CPUID(0xc0000000)
CPUID(0xc0000001)
(VII.) Previous iterations
--------------------------
Previous iterations of this work document the evolution of the call site
CPUID APIs. Please see:
(v5) https://lore.kernel.org/lkml/20250905121515.192792-1-darwi@linutronix.de
The cover letter there details the v1-v5 progression in full.
Thank you!
Ahmed
8<-----
base-commit: c369299895a591d96745d6492d4888259b004a9e
--
2.53.0
next reply other threads:[~2026-03-27 2:17 UTC|newest]
Thread overview: 149+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-27 2:15 Ahmed S. Darwish [this message]
2026-03-27 2:15 ` [PATCH v6 01/90] ASoC: Intel: avs: Check maximum valid CPUID leaf Ahmed S. Darwish
2026-03-27 9:26 ` Cezary Rojewski
2026-03-27 23:52 ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 02/90] ASoC: Intel: avs: Include CPUID header at file scope Ahmed S. Darwish
2026-03-27 9:25 ` Cezary Rojewski
2026-03-27 2:15 ` [PATCH v6 03/90] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v3.0 Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 04/90] treewide: Explicitly include the x86 CPUID headers Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 05/90] x86/cpu: <asm/processor.h>: Do not include the CPUID API header Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 06/90] x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 07/90] x86/cpuid: Introduce <asm/cpuid/leaf_types.h> Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 08/90] x86: Introduce a centralized CPUID data model Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 09/90] x86/cpuid: Introduce a centralized CPUID parser Ahmed S. Darwish
2026-04-15 6:09 ` Maciej Wieczor-Retman
2026-04-27 19:42 ` Ahmed S. Darwish
2026-04-28 15:03 ` Maciej Wieczor-Retman
2026-03-27 2:15 ` [PATCH v6 10/90] x86/cpu: Rescan CPUID table after disabling PSN Ahmed S. Darwish
2026-05-11 20:00 ` Borislav Petkov
2026-05-12 7:12 ` Ahmed S. Darwish
2026-05-12 14:34 ` Borislav Petkov
2026-05-13 15:27 ` Borislav Petkov
2026-05-13 16:06 ` Ahmed S. Darwish
2026-05-13 16:51 ` Borislav Petkov
2026-05-13 17:09 ` Borislav Petkov
2026-05-13 17:21 ` H. Peter Anvin
2026-05-13 17:25 ` Ahmed S. Darwish
2026-05-13 17:38 ` Borislav Petkov
2026-05-13 17:48 ` Ahmed S. Darwish
2026-05-14 4:47 ` Christian Ludloff
2026-05-13 15:57 ` Ahmed S. Darwish
2026-05-13 16:25 ` Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 11/90] x86/cpu: centaur/zhaoxin: Rescan CPUID(0xc0000001) after MSR writes Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 12/90] x86/cpu/transmeta: Rescan CPUID(0x1) after capability unhide Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 13/90] x86/cpu/intel: Rescan CPUID table after leaf unlock Ahmed S. Darwish
2026-04-15 12:36 ` Maciej Wieczor-Retman
2026-04-27 20:01 ` Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 14/90] x86/cpu: Use parsed CPUID(0x0) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 15/90] x86/lib: Add CPUID(0x1) family and model calculation Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 16/90] x86/cpu: Use parsed CPUID(0x1) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 17/90] x86/cpuid: Parse CPUID(0x80000000) Ahmed S. Darwish
2026-04-15 16:21 ` Maciej Wieczor-Retman
2026-03-27 2:15 ` [PATCH v6 18/90] x86/cpu: Use parsed CPUID(0x80000000) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 19/90] x86/cpuid: Parse CPUID(0x80000002) to CPUID(0x80000004) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 20/90] x86/cpu: Use parsed " Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 21/90] x86/cpuid: Split parser tables and add vendor-qualified parsing Ahmed S. Darwish
2026-04-15 19:45 ` Maciej Wieczor-Retman
2026-04-29 10:04 ` Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 22/90] x86/cpuid: Introduce a parser debugfs interface Ahmed S. Darwish
2026-04-15 20:34 ` Maciej Wieczor-Retman
2026-03-27 2:15 ` [PATCH v6 23/90] x86/cpuid: Parse CPUID(0x16) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 24/90] x86/tsc: Use parsed CPUID(0x16) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 25/90] x86/cpuid: Parse Transmeta and Centaur extended ranges Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 26/90] x86/cpu: transmeta: Use parsed CPUID(0x80860000)->CPUID(0x80860006) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 27/90] x86/cpu: transmeta: Refactor CPU information printing Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 28/90] x86/cpu: centaur: Use parsed CPUID(0xc0000001) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 29/90] x86/cpu: zhaoxin: " Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 30/90] x86/cpuid: Parse CPUID(0x2) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 31/90] x86/cpuid: Warn once on invalid CPUID(0x2) iteration count Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 32/90] x86/cpuid: Introduce parsed CPUID(0x2) API Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 33/90] x86/cpu: Use parsed CPUID(0x2) Ahmed S. Darwish
2026-04-16 19:16 ` Maciej Wieczor-Retman
2026-03-27 2:15 ` [PATCH v6 34/90] x86/cacheinfo: " Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 35/90] x86/cpuid: Remove direct CPUID(0x2) query helpers Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 36/90] x86/cpuid: Parse deterministic cache parameters CPUID leaves Ahmed S. Darwish
2026-04-17 9:20 ` Maciej Wieczor-Retman
2026-03-27 2:15 ` [PATCH v6 37/90] x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 38/90] x86/cacheinfo: Use parsed CPUID(0x4) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 39/90] x86/cacheinfo: Use parsed CPUID(0x8000001d) Ahmed S. Darwish
2026-04-17 14:47 ` Maciej Wieczor-Retman
2026-03-27 2:15 ` [PATCH v6 40/90] x86/cpuid: Parse CPUID(0x80000005), CPUID(0x80000006), CPUID(0x80000008) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 41/90] x86/cacheinfo: Use auto-generated data types Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 42/90] x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 43/90] x86/cacheinfo: Use parsed CPUID(0x80000006) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 44/90] x86/cpu: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2026-03-27 2:15 ` [PATCH v6 45/90] x86/cpu/amd: Use parsed CPUID(0x80000005) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 46/90] x86/cpu/amd: Refactor TLB detection code Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 47/90] x86/cpu/amd: Use parsed CPUID(CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 48/90] x86/cpu/hygon: Use parsed CPUID(0x80000005) " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 49/90] x86/cpu/centaur: Use parsed CPUID(0x80000005) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 50/90] x86/cpu: Use parsed CPUID(0x80000008) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 51/90] x86/cpuid: Parse CPUID(0xa) and CPUID(0x1c) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 52/90] x86/cpu/intel: Use parsed CPUID(0xa) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 53/90] x86/cpu/centaur: " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 54/90] x86/cpu/zhaoxin: " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 55/90] perf/x86/intel: " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 56/90] perf/x86/zhaoxin: " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 57/90] x86/xen: " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 58/90] KVM: x86: Use standard CPUID(0xa) types Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 59/90] KVM: x86/pmu: " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 60/90] perf/x86: Remove custom " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 61/90] perf/x86/lbr: Use parsed CPUID(0x1c) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 62/90] perf/x86/lbr: Remove custom CPUID(0x1c) types Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 63/90] x86/cpuid: Parse CPUID(0x23) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 64/90] perf/x86/intel: Use parsed per-CPU CPUID(0x23) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 65/90] perf/x86/intel: Remove custom CPUID(0x23) types Ahmed S. Darwish
2026-04-20 20:07 ` Maciej Wieczor-Retman
2026-03-27 2:16 ` [PATCH v6 66/90] x86/cpuid: Parse CPUID(0x80000022) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 67/90] perf/x86/amd/lbr: Use parsed CPUID(0x80000022) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 68/90] perf/x86/amd: " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 69/90] KVM: x86: Use standard CPUID(0x80000022) types Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 70/90] perf/x86: Remove custom " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 71/90] x86/cpuid: Parse CPUID(0x80000007) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 72/90] x86/cpu: Use parsed CPUID(0x80000007) Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 73/90] x86/cpu: amd/hygon: " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 74/90] x86/cpu: cpuinfo: " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 75/90] KVM: x86: " Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 76/90] x86/microcode: Allocate cpuinfo_x86 snapshots on the heap Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 77/90] x86/cpuid: Parse leaves backing X86_FEATURE words Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 78/90] x86/cpuid: Parse Linux synthetic CPUID leaves Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 79/90] x86/cpuid: Introduce a compile-time X86_FEATURE word map Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 80/90] x86/cpuid: Introduce X86_FEATURE and CPUID word APIs Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 81/90] x86/percpu: Add offset argument to x86_this_cpu_test_bit() Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 82/90] x86/cpufeature: Factor out a __static_cpu_has() helper Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 83/90] x86/asm/32: Cache CPUID(0x1).EDX in cpuid_table Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 84/90] x86: Route all feature queries to the CPUID tables Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 85/90] x86/cpu: Remove x86_capability[] and x86_power initialization Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 86/90] x86/cpu/transmeta: Remove x86_capability[] CPUID initialization Ahmed S. Darwish
2026-03-27 20:35 ` kernel test robot
2026-03-27 20:58 ` kernel test robot
2026-03-27 22:56 ` kernel test robot
2026-03-27 2:16 ` [PATCH v6 87/90] x86/cpu: centaur/zhaoxin: Remove x86_capability[] initialization Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 88/90] KVM: x86: Remove BUILD_BUG_ON() x86_capability[] check Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 89/90] x86/cpu: Remove x86_capability[] and x86_power Ahmed S. Darwish
2026-03-27 2:16 ` [PATCH v6 90/90] MAINTAINERS: Extend x86 CPUID DATABASE file coverage Ahmed S. Darwish
2026-03-27 15:23 ` [PATCH v6 00/90] x86: Introduce a centralized CPUID data model Borislav Petkov
2026-03-30 18:29 ` Ahmed S. Darwish
2026-03-30 23:08 ` Borislav Petkov
2026-04-13 14:03 ` Ahmed S. Darwish
2026-04-27 18:45 ` Ahmed S. Darwish
2026-05-05 13:33 ` Borislav Petkov
2026-05-05 15:12 ` Borislav Petkov
2026-05-05 19:11 ` Christian Ludloff
2026-05-06 8:50 ` Borislav Petkov
2026-05-06 13:59 ` H. Peter Anvin
2026-05-06 14:58 ` Borislav Petkov
2026-05-06 18:13 ` Christian Ludloff
2026-05-06 21:57 ` Ahmed S. Darwish
2026-05-06 22:18 ` Borislav Petkov
2026-05-06 23:03 ` Christian Ludloff
2026-05-06 20:52 ` Ahmed S. Darwish
2026-05-07 10:17 ` Borislav Petkov
2026-05-07 20:02 ` Ahmed S. Darwish
2026-04-07 10:09 ` Maciej Wieczor-Retman
2026-04-13 14:38 ` Ahmed S. Darwish
2026-04-21 17:27 ` Maciej Wieczor-Retman
2026-04-29 10:09 ` Ahmed S. Darwish
-- strict thread matches above, loose matches on Subject: below --
2026-04-07 8:55 Maciej Wieczor-Retman
2026-04-07 8:59 ` Borislav Petkov
2026-04-14 15:10 Maciej Wieczor-Retman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260327021645.555257-1-darwi@linutronix.de \
--to=darwi@linutronix.de \
--cc=andrew.cooper3@citrix.com \
--cc=bp@alien8.de \
--cc=dave.hansen@linux.intel.com \
--cc=dwmw2@infradead.org \
--cc=hpa@zytor.com \
--cc=john.ogness@linutronix.de \
--cc=linux-kernel@vger.kernel.org \
--cc=ludloff@gmail.com \
--cc=mingo@redhat.com \
--cc=peterz@infradead.org \
--cc=seanjc@google.com \
--cc=sohil.mehta@intel.com \
--cc=tglx@linutronix.de \
--cc=x86-cpuid@lists.linux.dev \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.