From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 1/6] drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable
Date: Fri, 12 Jun 2026 20:36:48 +0300 [thread overview]
Message-ID: <20260612173653.7830-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20260612173653.7830-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The GOP (and even Bspec on some platforms) is a bit inconsistent
on what the CDCLK_FREQ_DECIMAL divider should be. Currently any
mismatch there causes a full CDCLK PLL disable+re-enable, which
we really don't want to do if any displays are currently active.
Let's instead just reprogram CDCLK_FREQ_DECIMAL when that is the
only thing amiss. For any other (more serious) mismatch we still
punt to the full PLL reprogramming.
We also need to tweak the bxt_cdclk_cd2x_pipe() stuff a bit to
consistently select pipe==NONE since we have no idea which pipes
are enabled at this point. Since we're not actually changing the
CDCLK frequency here we don't need to sync the update to any
pipe.
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16209
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 41 ++++++++++++++++++----
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 189ae2d3cfc9..7bc9b956554b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1256,9 +1256,22 @@ static void skl_sanitize_cdclk(struct intel_display *display)
cdctl = intel_de_read(display, CDCLK_CTL);
expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
skl_cdclk_decimal(display->cdclk.hw.cdclk);
- if (cdctl == expected)
- /* All well; nothing to sanitize */
- return;
+
+ if (cdctl != expected) {
+ cdctl &= ~CDCLK_FREQ_DECIMAL_MASK;
+ cdctl |= expected & CDCLK_FREQ_DECIMAL_MASK;
+
+ if (cdctl != expected)
+ goto sanitize;
+
+ drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n",
+ intel_de_read(display, CDCLK_CTL), expected);
+
+ intel_de_write(display, CDCLK_CTL, expected);
+ }
+
+ /* All well; nothing to sanitize */
+ return;
sanitize:
drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
@@ -2354,11 +2367,25 @@ static void bxt_sanitize_cdclk(struct intel_display *display)
* (PIPE_NONE).
*/
cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
- expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
+ cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
- if (cdctl == expected)
- /* All well; nothing to sanitize */
- return;
+ if (cdctl != expected) {
+ if (DISPLAY_VER(display) < 20) {
+ cdctl &= ~CDCLK_FREQ_DECIMAL_MASK;
+ cdctl |= expected & CDCLK_FREQ_DECIMAL_MASK;
+ }
+
+ if (cdctl != expected)
+ goto sanitize;
+
+ drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n",
+ intel_de_read(display, CDCLK_CTL), expected);
+
+ intel_de_write(display, CDCLK_CTL, expected);
+ }
+
+ /* All well; nothing to sanitize */
+ return;
sanitize:
drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
--
2.53.0
next prev parent reply other threads:[~2026-06-12 17:37 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-12 17:36 [PATCH 0/6] drm/i915/cdclk: CDCLK sanitization stuff Ville Syrjala
2026-06-12 17:36 ` Ville Syrjala [this message]
2026-06-16 8:25 ` [PATCH 1/6] drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable Michał Grzelak
2026-06-12 17:36 ` [PATCH 2/6] drm/i915/cdclk: Print the reason for the CDCLK sanitization Ville Syrjala
2026-06-16 8:25 ` Michał Grzelak
2026-06-12 17:36 ` [PATCH 3/6] drm/i915/cdclk Clean up CDCLK_CTL defines Ville Syrjala
2026-06-16 8:26 ` Michał Grzelak
2026-06-12 17:36 ` [PATCH 4/6] drm/i915/cdclk: Document CDCLK_CTL bits Ville Syrjala
2026-06-16 8:26 ` Michał Grzelak
2026-06-12 17:36 ` [PATCH 5/6] drm/i915/cdclk: Introduce bxt_cdclk_cd2x_pipe_mask() and use it Ville Syrjala
2026-06-16 8:26 ` Michał Grzelak
2026-06-12 17:36 ` [PATCH 6/6] drm/i915/cdclk: Use the TGL+ CD2x pipe select bits also on ICL Ville Syrjala
2026-06-16 8:26 ` Michał Grzelak
2026-06-12 18:43 ` ✗ CI.checkpatch: warning for drm/i915/cdclk: CDCLK sanitization stuff Patchwork
2026-06-12 18:45 ` ✓ CI.KUnit: success " Patchwork
2026-06-12 18:51 ` ✓ i915.CI.BAT: " Patchwork
2026-06-12 19:38 ` ✓ Xe.CI.BAT: " Patchwork
2026-06-13 12:38 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-06-13 16:17 ` ✗ i915.CI.Full: " Patchwork
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