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    TeaRex, thank you for the detailed info. I am confused on a major issue, though. You state that CP/M writes to the screen do NOT go thru the 8502 CPU, but the CP/M chapter of the C128 Programmer's Reference Guide seems to state otherwise. I quoted a section which begins with the sentence, "The 8502 is responsible for most of the low-level I/O functions." It seems very strange that they would use the word "most" yet include neither screen nor keyboard I/O in this. I am not saying you are wrong, just that if you are correct, official docs are misleading. Commented Feb 7, 2020 at 13:35
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    @RichF, maybe the C128 PRG was (partially) written before the CP/M code had been finalized? You can look at the code yourself to see what it does. Commented Feb 7, 2020 at 14:02
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    Thanks for helping me understand better the major issues and which ones were readily (vs. not so much) solvable. Knowing that C128 FAST mode doesn't work in CP/M explains a lot. Commented Apr 14, 2020 at 14:58
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    CP/M Plus character device reassignment is handled in the BIOS, not the BDOS. Though it's entirely possible that Commodore simply copied the 8080 code from Digital Research's sample BIOS as printed in the CP/M 3 System Guide. Commented Mar 14, 2023 at 12:49
  • In normal mode, the VIC-IIe would perform DRAM refresh cycles during its half of some of the memory cycles on each scan line. I don't know how such cycles are handled in fast mode, would not be surprised if they fail to occur in fast mode when using the Z80. I also don't know whether DRAM rows use upper or lower address bits--or whether a sequence of 51 e.g. "LD HL,(009Ah) / LD HL,(0x009Ch) / LD (HL,0x009Eh) / etc. up to LD HL,00FEh" and a "RET" starting at byte 0 of a page could be executed every couple milliseconds to ensure every row gets hit, or whether something more like... Commented Jun 15, 2024 at 18:38