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High-Performance Fully Depleted Silicon Nanowire (Diameter ≤ 5 Nm) Gate-All-Around CMOS Devices

Abstract

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with $\leq$ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope ($\sim$ 63 mV/dec), low drain-induced barrier lowering ($\sim$ 10 mV/V), and with $I_{\rm ON}/I_{\rm OFF}$ ratio of $\sim10^{6}$. High drive currents of $\sim$ 1.5 and $\sim1.0\ \hbox{mA}/\mu\hbox{m}$ were achieved for 180-nm-long n- and p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.


Publication:
IEEE Electron Device Letters
Pub Date:
2006
DOI:

10.1109/LED.2006.873381

Bibcode:
2006IEDL...27..383S
Keywords:
  • CMOS-compatible process;
  • gate-all-around (GAA);
  • silicon nanowire transistor;
  • surround gate;
  • wrap-around-gate
full text sources
IEEE
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