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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-04-01 22:00:37 -0700 |
|---|---|---|
| committer | Luc Van Oostenryck <luc.vanoostenryck@gmail.com> | 2022-06-05 22:07:23 +0200 |
| commit | 90feaaa967227961fc9972a0a46bb4fa51eec7b2 (patch) | |
| tree | 683ec0180b0b7853e118a39858a92ba9e8d30487 /opcode.c | |
| parent | e31e645f5c29b6587404c1efe534c65b4691e023 (diff) | |
| download | sparse-dev-90feaaa967227961fc9972a0a46bb4fa51eec7b2.tar.gz | |
RISC-V: Match GCC's semantics for multiple -march instances
GCC's semantics for "-march=X -march=Y" are that Y entirely overrides X,
but sparse takes the union of these two ISA strings. This fixes the
behavior by setting, instead of oring, the flags whenever a base ISA is
encountered. RISC-V ISA strings can only have a single base ISA, it's
not like x86 where the 64-bit ISA is an extension of the 32-bit ISA.
[Luc Van Oostenryck: reset the flags at the start of the parsing loop]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
Diffstat (limited to 'opcode.c')
0 files changed, 0 insertions, 0 deletions