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| author | Luc Van Oostenryck <luc.vanoostenryck@gmail.com> | 2021-03-12 01:06:54 +0100 |
|---|---|---|
| committer | Luc Van Oostenryck <luc.vanoostenryck@gmail.com> | 2021-03-12 01:09:54 +0100 |
| commit | c089cd2dc771e5bf175a390966e454df3334955d (patch) | |
| tree | 826abdf09752fd0c2bcbb7f9b2c2b26010e8656d /validation/optim/cmpu-and0.c | |
| parent | d549d4d55eecb394e3f69314287f91e85b19e3e3 (diff) | |
| parent | eb4cdd21b7d0cedbbeff7f70e24473706ccce5a6 (diff) | |
| download | sparse-dev-c089cd2dc771e5bf175a390966e454df3334955d.tar.gz | |
Merge branches 'fix-ssa' and 'cmp-and-or' into next
* fix SSA conversion of mismatched memops
* simplify CMP(AND(x,M), C) and CMP(OR(x,M), C)
Diffstat (limited to 'validation/optim/cmpu-and0.c')
| -rw-r--r-- | validation/optim/cmpu-and0.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/validation/optim/cmpu-and0.c b/validation/optim/cmpu-and0.c new file mode 100644 index 00000000..927b9fb6 --- /dev/null +++ b/validation/optim/cmpu-and0.c @@ -0,0 +1,17 @@ +#define MASK 32U + + +int cmps_and_ltu_gt(int a) { return ((a & MASK) < (MASK + 1)) + 0; } +int cmps_and_leu_gt(int a) { return ((a & MASK) <= (MASK + 1)) + 0; } +int cmps_and_leu_eq(int a) { return ((a & MASK) <= (MASK + 0)) + 0; } +int cmps_and_geu_gt(int a) { return ((a & MASK) >= (MASK + 1)) + 1; } +int cmps_and_gtu_gt(int a) { return ((a & MASK) > (MASK + 1)) + 1; } +int cmps_and_gtu_eq(int a) { return ((a & MASK) > (MASK + 0)) + 1; } + +/* + * check-name: cmpu-and0 + * check-command: test-linearize -Wno-decl $file + * + * check-output-ignore + * check-output-returns: 1 + */ |