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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2026-06-15 13:34:03 +0530 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2026-06-15 13:34:03 +0530 |
| commit | f20e2fdaaeb74330a6c5d65af22a8c47409a7a91 (patch) | |
| tree | 73497c6bd12008e52c96e54d4e1e79032bdda1b5 /Documentation | |
| parent | 9e94480d81b9eb9bd175499636bf622e5d62176d (diff) | |
| parent | c66494c79ede1af529dbf67f9ed6fdbf42e05ef3 (diff) | |
| download | ath-f20e2fdaaeb74330a6c5d65af22a8c47409a7a91.tar.gz | |
Merge tag 'timers-clocksource-2026-06-13' of gitolite.kernel.org:pub/scm/linux/kernel/git/tip/tip
Pull clocksource updates from Thomas Gleixner:
"Updates for clocksource/clockevent drivers:
- Add devm helpers for clocksources, which allows to simplify driver
teardown and probe failure handling.
- More module conversion work
- Update the support for the ARM EL2 virtual timer including the
required ACPI changes.
- Add clockevent and clocksource support for the TI Dual Mode Timer
- Fix the support for multiple watchdog instances in the TEGRA186
driver
- Add D1 timer support to the SUN5I driver
- The usual devicetree updates, cleanups and small fixes all over the
place"
* tag 'timers-clocksource-2026-06-13' of gitolite.kernel.org:pub/scm/linux/kernel/git/tip/tip: (24 commits)
clocksource: move NXP timer selection to drivers/clocksource
clocksource/drivers/timer-tegra186: Reserve and service a kernel watchdog
clocksource/drivers/timer-tegra186: Register all accessible watchdog timers
clocksource/drivers/timer-tegra186: Correct num_wdts for Tegra186 and Tegra234
clocksource/drivers/timer-tegra186: Fix support for multiple watchdog instances
clocksource/drivers/timer-ti-dm: Add clockevent support
clocksource/drivers/timer-ti-dm: Add clocksource support
clocksource/drivers/timer-ti-dm: Fix property name in comment
dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt description
clocksource/drivers/arm_arch_timer: Default to EL2 virtual timer when running VHE
ACPI: GTDT: Parse information related to the EL2 virtual timer
ACPI: GTDT: Account for GTDTv3 size when walking the platform timer descriptors
clocksource: Add devm_clocksource_register_*() helpers
clocksource/drivers/sun5i: Add D1 hstimer support
dt-bindings: timer: allwinner,sun5i-a13-hstimer: add H616 and D1
dt-bindings: timer: Add StarFive JHB100 clint
dt-bindings: timer: renesas,rz-mtu3: document RZ/{T2H,N2H}
dt-bindings: timer: renesas,rz-mtu3: Remove TCIU8 interrupt
dt-bindings: timer: Remove sifive,fine-ctr-bits property
clocksource/drivers/timer-of: Make the code compatible with modules
...
Diffstat (limited to 'Documentation')
5 files changed, 38 insertions, 36 deletions
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml index f1853daec2f9a..3e2725c569953 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml @@ -15,9 +15,13 @@ properties: oneOf: - const: allwinner,sun5i-a13-hstimer - const: allwinner,sun7i-a20-hstimer + - const: allwinner,sun20i-d1-hstimer - items: - const: allwinner,sun6i-a31-hstimer - const: allwinner,sun7i-a20-hstimer + - items: + - const: allwinner,sun50i-h616-hstimer + - const: allwinner,sun20i-d1-hstimer reg: maxItems: 1 @@ -45,7 +49,10 @@ required: if: properties: compatible: - const: allwinner,sun5i-a13-hstimer + anyOf: + - const: allwinner,sun5i-a13-hstimer + - contains: + const: allwinner,sun20i-d1-hstimer then: properties: diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml index c5fc3b6c8bd0b..c65e48a155ab6 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml @@ -10,13 +10,8 @@ maintainers: - Marc Zyngier <marc.zyngier@arm.com> - Mark Rutland <mark.rutland@arm.com> description: |+ - ARM cores may have a per-core architected timer, which provides per-cpu timers, - or a memory mapped architected timer, which provides up to 8 frames with a - physical and optional virtual timer per frame. - - The per-core architected timer is attached to a GIC to deliver its - per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC - to deliver its interrupts via SPIs. + The per-core architected timer is expected to deliver per-CPU interrupts + (commonly to a GIC to deliver its per-processor interrupts as PPIs). properties: compatible: @@ -33,13 +28,13 @@ properties: - const: arm,armv7-timer interrupts: - minItems: 1 + minItems: 2 items: - - description: secure timer irq - - description: non-secure timer irq - - description: virtual timer irq - - description: hypervisor timer irq - - description: hypervisor virtual timer irq + - description: EL1 secure physical timer irq, if EL3 is implemented + - description: EL1 non-secure physical timer irq + - description: EL1 virtual timer irq + - description: EL2 physical timer irq, if EL2 is implemented + - description: EL2 virtual timer irq, if FEAT_VHE is implemented interrupt-names: oneOf: diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml index 9898dc7ea97be..6d41fb1203793 100644 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml @@ -14,6 +14,7 @@ properties: oneOf: - const: fsl,imx1-gpt - const: fsl,imx21-gpt + - const: fsl,imx25-epit - items: - const: fsl,imx27-gpt - const: fsl,imx21-gpt diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml index 3ad10c5b66ba5..ecff2912d812b 100644 --- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml @@ -112,6 +112,8 @@ properties: - renesas,r9a07g043-mtu3 # RZ/{G2UL,Five} - renesas,r9a07g044-mtu3 # RZ/G2{L,LC} - renesas,r9a07g054-mtu3 # RZ/V2L + - renesas,r9a09g077-mtu3 # RZ/T2H + - renesas,r9a09g087-mtu3 # RZ/N2H - const: renesas,rz-mtu3 reg: @@ -162,7 +164,6 @@ properties: - description: MTU8.TGRC input capture/compare match - description: MTU8.TGRD input capture/compare match - description: MTU8.TCNT overflow - - description: MTU8.TCNT underflow interrupt-names: items: @@ -209,7 +210,6 @@ properties: - const: tgic8 - const: tgid8 - const: tciv8 - - const: tciu8 clocks: maxItems: 1 @@ -233,7 +233,22 @@ required: - interrupt-names - clocks - power-domains - - resets + +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a07g043-mtu3 + - renesas,r9a07g044-mtu3 + - renesas,r9a07g054-mtu3 + then: + required: + - resets + else: + properties: + resets: false additionalProperties: false @@ -287,8 +302,7 @@ examples: <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>; interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0", "tgif0", "tgia1", "tgib1", "tciv1", "tciu1", @@ -298,7 +312,7 @@ examples: "tgiu5", "tgiv5", "tgiw5", "tgia6", "tgib6", "tgic6", "tgid6", "tciv6", "tgia7", "tgib7", "tgic7", "tgid7", "tciv7", - "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8"; + "tgia8", "tgib8", "tgic8", "tgid8", "tciv8"; clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3c16b260db040..67cea8edb59f5 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -38,6 +38,7 @@ properties: - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 + - starfive,jhb100-clint # StarFive JHB100 - tenstorrent,blackhole-clint # Tenstorrent Blackhole - const: sifive,clint0 # SiFive CLINT v0 IP block - items: @@ -72,22 +73,6 @@ properties: minItems: 1 maxItems: 4095 - sifive,fine-ctr-bits: - maximum: 15 - description: The width in bits of the fine counter. - -if: - properties: - compatible: - contains: - const: sifive,clint2 -then: - required: - - sifive,fine-ctr-bits -else: - properties: - sifive,fine-ctr-bits: false - additionalProperties: false required: |