| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2026-06-10 | cxl/port: update reference to removed CONFIG_PROVE_CXL_LOCKING | Ethan Nelson-Moore | 1 | -1/+1 |
| 2026-02-02 | Merge branch 'for-7.0/cxl-aer-prep' into cxl-for-next | Dave Jiang | 1 | -0/+122 |
| 2026-02-02 | cxl/port: Move endpoint component register management to cxl_port | Dan Williams | 1 | -0/+54 |
| 2026-02-02 | cxl/port: Map Port RAS registers | Terry Bowman | 1 | -0/+6 |
| 2026-02-02 | cxl/port: Move dport RAS setup to dport add time | Dan Williams | 1 | -0/+12 |
| 2026-02-02 | cxl/port: Move dport probe operations to a driver event | Dan Williams | 1 | -0/+50 |
| 2026-01-05 | cxl/port: Arrange for always synchronous endpoint attach | Dan Williams | 1 | -0/+40 |
| 2025-09-18 | cxl: Defer dport allocation for switch ports | Dave Jiang | 1 | -8/+3 |
| 2025-09-18 | cxl/test: Refactor decoder setup to reduce cxl_test burden | Dave Jiang | 1 | -36/+2 |
| 2025-06-17 | sysfs: treewide: switch back to attribute_group::bin_attrs | Thomas Weißschuh | 1 | -1/+1 |
| 2025-05-09 | cxl/region: Move find_cxl_root() to cxl_add_to_region() | Robert Richter | 1 | -12/+3 |
| 2025-02-21 | cxl/port: Constify 'struct bin_attribute' | Thomas Weißschuh | 1 | -5/+5 |
| 2025-01-02 | cxl/pci: Add CXL Type 1/2 support to cxl_dvsec_rr_decode() | Alejandro Lucero | 1 | -1/+1 |
| 2024-12-02 | module: Convert symbol namespace to string literal | Peter Zijlstra | 1 | -1/+1 |
| 2024-11-05 | sysfs: treewide: constify attribute callback of bin_is_visible() | Thomas Weißschuh | 1 | -1/+1 |
| 2024-10-25 | cxl/port: Fix CXL port initialization order when the subsystem is built-in | Dan Williams | 1 | -1/+16 |
| 2024-09-09 | cxl/pci: Remove duplicated implementation of waiting for memory_info_valid | Yanfei Xu | 1 | -1/+1 |
| 2024-07-02 | cxl: add missing MODULE_DESCRIPTION() macros | Jeff Johnson | 1 | -0/+1 |
| 2024-01-05 | cxl: Refactor to use __free() for cxl_root allocation in cxl_endpoint_port_pr... | Dave Jiang | 1 | -3/+2 |
| 2024-01-05 | cxl: Convert find_cxl_root() to return a 'struct cxl_root *' | Dave Jiang | 1 | -1/+3 |
| 2023-12-22 | cxl: Add callback to parse the SSLBIS subtable from CDAT | Dave Jiang | 1 | -0/+2 |
| 2023-12-22 | cxl: Add callback to parse the DSMAS subtables from CDAT | Dave Jiang | 1 | -0/+1 |
| 2023-10-27 | cxl: Add support for reading CXL switch CDAT table | Dave Jiang | 1 | -0/+3 |
| 2023-06-25 | Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl | Dan Williams | 1 | -2/+5 |
| 2023-06-25 | Revert "cxl/port: Enable the HDM decoder capability for switch ports" | Dan Williams | 1 | -9/+5 |
| 2023-06-25 | cxl/regs: Remove early capability checks in Component Register setup | Robert Richter | 1 | -1/+4 |
| 2023-06-25 | cxl: Rename 'uport' to 'uport_dev' | Dan Williams | 1 | -1/+1 |
| 2023-05-18 | cxl: Move cxl_await_media_ready() to before capacity info retrieval | Dave Jiang | 1 | -6/+0 |
| 2023-05-18 | cxl/port: Enable the HDM decoder capability for switch ports | Dan Williams | 1 | -5/+9 |
| 2023-04-18 | cxl/port: Scan single-target ports for decoders | Dan Williams | 1 | -5/+13 |
| 2023-04-04 | cxl/port: Fix find_cxl_root() for RCDs and simplify it | Dan Williams | 1 | -1/+1 |
| 2023-04-04 | cxl/hdm: Skip emulation when driver manages mem_enable | Dan Williams | 1 | -1/+1 |
| 2023-02-14 | Merge branch 'for-6.3/cxl-rr-emu' into cxl/next | Dan Williams | 1 | -5/+10 |
| 2023-02-14 | cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decoders | Dave Jiang | 1 | -1/+1 |
| 2023-02-14 | cxl/hdm: Emulate HDM decoder from DVSEC range registers | Dave Jiang | 1 | -1/+1 |
| 2023-02-14 | cxl/port: Export cxl_dvsec_rr_decode() to cxl_port | Dave Jiang | 1 | -7/+13 |
| 2023-02-10 | cxl/region: Add region autodiscovery | Dan Williams | 1 | -1/+46 |
| 2023-02-10 | cxl/port: Split endpoint and switch port probe | Dan Williams | 1 | -30/+39 |
| 2022-07-19 | cxl/port: Read CDAT table | Ira Weiny | 1 | -0/+53 |
| 2022-05-19 | cxl/port: Reuse 'struct cxl_hdm' context for hdm init | Dan Williams | 1 | -11/+14 |
| 2022-05-19 | cxl/port: Move endpoint HDM Decoder Capability init to port driver | Dan Williams | 1 | -0/+11 |
| 2022-02-08 | cxl/core/port: Add endpoint decoders | Ben Widawsky | 1 | -8/+9 |
| 2022-02-08 | cxl/mem: Add the cxl_mem driver | Ben Widawsky | 1 | -0/+12 |
| 2022-02-08 | cxl/core/port: Remove @host argument for dport + decoder enumeration | Dan Williams | 1 | -4/+4 |
| 2022-02-08 | cxl/port: Add a driver for 'struct cxl_port' objects | Ben Widawsky | 1 | -0/+63 |
