diff options
| author | Mark Brown <broonie@kernel.org> | 2026-05-29 18:08:30 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-05-29 18:08:30 +0100 |
| commit | 798b33e57c69de98c8f62c3508a38b6de5396223 (patch) | |
| tree | 187bd37e0c8a21e3e00b8cb7065a4f6b561e085b | |
| parent | 4a1c81dc8d0043f695f4bc53c1265636c8fd46fe (diff) | |
| parent | 9318b3b22e833b5edcd378d28c64b4f88a801b7b (diff) | |
| download | linux-next-history-798b33e57c69de98c8f62c3508a38b6de5396223.tar.gz | |
Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
91 files changed, 2419 insertions, 823 deletions
diff --git a/Documentation/arch/arm/index.rst b/Documentation/arch/arm/index.rst index afe17db294c4a..b15621093f7a2 100644 --- a/Documentation/arch/arm/index.rst +++ b/Documentation/arch/arm/index.rst @@ -75,3 +75,5 @@ SoC-specific documents sti/overview vfp/release-notes + + zte/index diff --git a/Documentation/arch/arm/zte/index.rst b/Documentation/arch/arm/zte/index.rst new file mode 100644 index 0000000000000..0ed80b60b7463 --- /dev/null +++ b/Documentation/arch/arm/zte/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +======= +ZTE SoC +======= + +.. toctree:: + :maxdepth: 1 + + zx297520v3 diff --git a/Documentation/arch/arm/zte/zx297520v3.rst b/Documentation/arch/arm/zte/zx297520v3.rst new file mode 100644 index 0000000000000..2122887e391aa --- /dev/null +++ b/Documentation/arch/arm/zte/zx297520v3.rst @@ -0,0 +1,167 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +==================================== +Booting Linux on ZTE zx297520v3 SoCs +==================================== + +............................................................................... + +Author: Stefan Dösinger + +Date : 27 Jan 2026 + +1. Hardware description +--------------------------- +Zx297520v3 SoCs use a 64 bit capable Cortex-A53 CPU and GICv3, although they +run in arm32 mode only. The CPU has support EL3, but no hypervisor (EL2) and +it seems to lack VFP and NEON. + +The SoC is used in a number of cheap LTE to WiFi routers, both battery powered +MiFis and stationary CPEs. In addition to the CPU these devices usually have +64 MB Ram (although some is shared with the LTE chip), 128 MB NAND flash, an +SDIO connected RTL8192-type Wifi chip limited to 2.4 ghz operation, USB 2, +and buttons. Devices with as low as 32 MB or as high as 128 MB ram exist, as +do devices with 8 or 16 MB of NOR flash. + +Some devices, especially the stationary ones, have 100 mbit Ethernet and an +Ethernet switch. + +Usually the devices have LEDs for status indication, although some have SPI or +I2C connected displays + +Some have an SD card slot. If it exists, it is a better choice for the root +file system because it easily outperforms the built-in NAND. + +The LTE interface runs on a separate DSP called ZSP880. It is probably derived +from LSI ZSPs and has an undocumented instruction set. The ZSP communicates +with the main CPU via SRAM and DRAM and a mailbox hardware that can generate +IRQs on either ends. + +There is also a Cortex M0 CPU, which is responsible for early HW initialization +and starting the Cortex A53 CPU. It does not have any essential purpose once +U-Boot is started. A SRAM-Based handover protocol exists to run custom code on +this CPU. + +2. Booting via USB +--------------------------- + +The Boot ROM has support for booting custom code via USB. This mode can be +entered by connecting a Boot PIN to GND or by modifying the third byte on NAND +(set it to anything other than 0x5A aka 'Z'). A free software tool to start +custom U-Boot and kernels can be found here: + +https://github.com/zx297520v3-mainline/zx297520v3-loader + +If USB download mode is entered but no boot commands are sent through USB, the +device will proceed to boot normally after a few seconds. It is therefore +possible to enable USB boot permanently and still leave the default boot files +in place. + +https://github.com/zx297520v3-mainline/u-boot-mainline + +Contains an U-Boot version that can be used with the USB loader and sets up the +CPU and interrupt controller to comply with Linux's booting requirements. + +3. Building for built-in U-Boot +--------------------------- +The devices come with an ancient U-Boot that loads legacy uImages from NAND and +boots them without a chance for the user to interrupt. The images are stored in +files ap_cpuap.bin and ap_recovery.bin on a jffs2 partition named imagefs, +usually mtd4. A file named "fotaflag" switches between the two modes. + +In addition to the uImage header, those files have a 384 byte signature header, +which is used for authenticating the images on some devices. Most devices have +this authentication disabled and it is enough to pad the uImage files with 384 +zero bytes. + +Builtin U-Boot also poorly sets up the CPU. Read the next section for details +on this. It has no support for loading DTBs, so CONFIG_ARM_APPENDED_DTB is +needed. + +So to build an image that boots from NAND the following steps are necessary: + +1) Patch the assembly code from section 3 into arch/arm/kernel/head.S. +2) make zx29_defconfig +3) make [-j x] +4) cat arch/arm/boot/zImage arch/arm/boot/dts/zte/[device].dtb > kernel+dtb +5) mkimage -A arm -O linux -T kernel -C none -a 0x20008000 -d kernel+dtb uimg +6) dd if=/dev/zero bs=1 count=384 of=ap_recovery.bin +7) cat uimg >> ap_recovery.bin +8) Place this file onto imagefs on the device. Delete ap_cpuap.bin if the +free space is not enough. +9) Create the file fotaflag: echo -n FOTA-RECOVERY > fotaflag + +For development, booting ap_recovery.bin is recommended because the normal boot +mode arms the watchdog before starting the kernel. + +4. CPU and GIC Setup +--------------------------- + +Generally CPU and GICv3 need to be set up according to the requirements spelled +out in Documentation/arch/arm64/booting.rst. For zx297520v3 this means: + +1. GICD_CTLR.DS=1 to disable GIC security +2. Enable access to ICC_SRE +3. Disable trapping IRQs into monitor mode +4. Configure EL2 and below to run in insecure mode. +5. Configure timer PPIs to active-low. + +The kernel sources provided by ZTE do not boot either (interrupts do not work +at all). They are incomplete in other aspects too, so it is assumed that there +is some workaround similar to the one described in this document somewhere in +the binary blobs. + +The assembly code below is given as an example of how to achieve this: + +``` +#include <linux/irqchip/arm-gic-v3.h> +#include <asm/assembler.h> +#include <asm/cp15.h> + +@ Detect sane bootloaders and skip the hack +ldr r3, =0xf2000000 +ldr r3, [r3] +ldr r4, =(GICD_CTLR_ARE_NS | GICD_CTLR_DS) +cmp r3, r4 +beq skip_zx_hack +@ This allows EL1 to handle ints hat are normally handled by EL2/3. +ldr r3, =0xf2000000 +str r4, [r3] + +cps #MON_MODE + +@ Work in non-secure physical address space: SCR_EL3.NS = 1. At least the UART +@ seems to respond only to non-secure addresses. I have taken insipiration from +@ Raspberry pi's armstub7.S here. +mov r3, #0x131 @ non-secure, Make F, A bits in CPSR writeable + @ Allow hypervisor call. +mcr p15, 0, r3, c1, c1, 0 + +@ AP_PPI_MODE_REG: Configure timer PPIs (10, 11, 13, 14) to active-low. +ldr r3, =0xF22020a8 +ldr r4, =0x50 +str r4, [r3] +ldr r3, =0xF22020ac +ldr r4, =0x14 +str r4, [r3] + +@ Enable EL2 access to ICC_SRE (bit 3, ICC_SRE_EL3.Enable). Enable system reg +@ access to GICv3 registers (bit 0, ICC_SRE_EL3.SRE) for EL1 and EL3. +mrc p15, 6, r3, c12, c12, 5 @ ICC_SRE_EL3 +orr r3, #0x9 @ FIXME: No defines for SRE_EL3 values? +mcr p15, 6, r3, c12, c12, 5 +mrc p15, 0, r3, c12, c12, 5 @ ICC_SRE_EL1 +orr r3, #(ICC_SRE_EL1_SRE) +mcr p15, 0, r3, c12, c12, 5 + +@ Like ICC_SRE_EL3, enable EL1 access to ICC_SRE and system register access +@ for EL2. +mrc p15, 4, r3, c12, c9, 5 @ ICC_SRE_EL2 aka ICC_HSRE +orr r3, r3, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE) +mcr p15, 4, r3, c12, c9, 5 +isb + +@ Back to SVC mode +cps #SVC_MODE +skip_zx_hack: +``` diff --git a/Documentation/devicetree/bindings/arm/zte.yaml b/Documentation/devicetree/bindings/arm/zte.yaml new file mode 100644 index 0000000000000..f028d2cec7ab2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/zte.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx platforms + +maintainers: + - Stefan Dösinger <stefandoesinger@gmail.com> + +description: | + ARM platforms using SoCs designed by ZTE. Currently this supports devices + based on the zx297520v3 SoC which is found in LTE routers. + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - items: + - enum: + - dlink,dwr932m + - const: zte,zx297520v3 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml index a0e09b7002f07..703b5bf26717c 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml @@ -41,7 +41,7 @@ properties: clock-output-names: minItems: 3 - maxItems: 17 + maxItems: 19 renesas,mode: description: Board-specific settings of the MD_CK* bits on R-Mobile A1 @@ -90,6 +90,8 @@ allOf: - const: zx - const: zs - const: hp + - const: ztr + - const: zt - if: properties: @@ -123,6 +125,8 @@ allOf: - const: zb - const: m3 - const: cp + - const: ztr + - const: zt required: - renesas,mode @@ -240,6 +244,6 @@ examples: #clock-cells = <1>; clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b", "m1", "hp", "hpp", - "usbp", "s", "zb", "m3", "cp"; + "usbp", "s", "zb", "m3", "cp", "ztr", "zt"; renesas,mode = <0x05>; }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 00c05243b9a47..fb1fe1ea759fc 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a08g046-pinctrl # RZ/G3L - renesas,r9a09g047-pinctrl # RZ/G3E - renesas,r9a09g056-pinctrl # RZ/V2N - renesas,r9a09g057-pinctrl # RZ/V2H(P) @@ -78,6 +79,26 @@ properties: - description: PFC main reset - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins + reset-names: + oneOf: + - items: + - const: rstn + - const: port + - const: spare + - items: + - const: main + - const: error + + renesas,clonech: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to system controller + - description: offset of clone channel control register + description: + Phandle and offset to the system controller containing the clone channel + control values. + additionalProperties: anyOf: - type: object @@ -144,6 +165,15 @@ allOf: properties: compatible: contains: + const: renesas,r9a08g046-pinctrl + then: + required: + - renesas,clonech + + - if: + properties: + compatible: + contains: enum: - renesas,r9a09g047-pinctrl - renesas,r9a09g056-pinctrl @@ -152,10 +182,14 @@ allOf: properties: resets: maxItems: 2 + reset-names: + maxItems: 2 else: properties: resets: minItems: 3 + reset-names: + minItems: 3 required: - compatible @@ -187,6 +221,7 @@ examples: resets = <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; power-domains = <&cpg>; scif0_pins: serial0 { diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml new file mode 100644 index 0000000000000..eef8c0a59e9c0 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,r8a78000-mfis.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas MFIS (Multifunctional Interface) controller + +maintainers: + - Wolfram Sang <wsa+renesas@sang-engineering.com> + +description: + The Renesas Multifunctional Interface (MFIS) provides various functionality + like mailboxes, hardware spinlocks, product identification, error injection, + error detection and such. Parts of it can be used for communication between + different CPU cores. Those cores can be in various domains like AP, RT, or + SCP. Often multiple domain-specific MFIS instances exist in one SoC. + +properties: + compatible: + enum: + - renesas,r8a78000-mfis # R-Car X5H (AP<->AP, with PRR) + - renesas,r8a78000-mfis-scp # R-Car X5H (AP<->SCP, without PRR) + + reg: + maxItems: 2 + + reg-names: + items: + - const: common + - const: mboxes + + interrupts: + minItems: 32 + maxItems: 128 + description: + The interrupts raised by the remote doorbells. + + interrupt-names: + minItems: 32 + maxItems: 128 + description: + An interrupt name is constructed with the prefix 'ch'. Then, the + channel number as specified in the documentation of the SoC. Finally, + the letter 'i' if the interrupt is raised by the IICR register. Or 'e' + if it is raised by the EICR register. + + "#hwlock-cells": + const: 1 + + "#mbox-cells": + const: 2 + description: + The first cell is the channel number as specified in the documentation + of the SoC. The second cell may specify flags as described in the file + <dt-bindings/soc/renesas,r8a78000-mfis.h>. + +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r8a78000-mfis + then: + properties: + interrupts: + minItems: 128 + interrupt-names: + minItems: 128 + items: + pattern: "^ch[0-9]+[ie]$" + + - if: + properties: + compatible: + contains: + const: renesas,r8a78000-mfis-scp + then: + properties: + interrupts: + maxItems: 32 + interrupt-names: + maxItems: 32 + items: + pattern: "^ch[0-9]+i$" + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - "#hwlock-cells" + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + system-controller@189e0000 { + compatible = "renesas,r8a78000-mfis"; + reg = <0x189e0000 0x1000>, <0x18800000 0x40000>; + reg-names = "common", "mboxes"; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e", + "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e", + "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e", + "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e", + "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e", + "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e", + "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e", + "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e", + "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e", + "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e", + "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e", + "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e", + "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e", + "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e", + "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e", + "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e"; + #hwlock-cells = <1>; + #mbox-cells = <2>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 318b1b6772783..3d605df0b895b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3791,6 +3791,15 @@ F: drivers/video/fbdev/vt8500lcdfb.* F: drivers/video/fbdev/wm8505fb* F: drivers/video/fbdev/wmt_ge_rops.* +ARM/ZTE ZX29 SOC SUPPORT +M: Stefan Dösinger <stefandoesinger@gmail.com> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Odd fixes +F: Documentation/arch/arm/zte/ +F: Documentation/devicetree/bindings/arm/zte.yaml +F: arch/arm/boot/dts/zte/ +F: arch/arm/mach-zte/ + ARM/ZYNQ ARCHITECTURE M: Michal Simek <michal.simek@amd.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 73e6647bea463..fc398730336ea 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -465,6 +465,8 @@ source "arch/arm/mach-versatile/Kconfig" source "arch/arm/mach-vt8500/Kconfig" +source "arch/arm/mach-zte/Kconfig" + source "arch/arm/mach-zynq/Kconfig" # ARMv7-M architecture diff --git a/arch/arm/Makefile b/arch/arm/Makefile index b7de4b6b284ca..573813ef5e77a 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -223,6 +223,7 @@ machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_U8500) += ux500 machine-$(CONFIG_ARCH_VT8500) += vt8500 +machine-$(CONFIG_ARCH_ZTE) += zte machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_PLAT_VERSATILE) += versatile machine-$(CONFIG_PLAT_SPEAR) += spear diff --git a/arch/arm/arm-soc-for-next-contents.txt b/arch/arm/arm-soc-for-next-contents.txt new file mode 100644 index 0000000000000..298bd47edb1d1 --- /dev/null +++ b/arch/arm/arm-soc-for-next-contents.txt @@ -0,0 +1,67 @@ +soc/arm + patch + ARM: select legacy gpiolib interfaces where used + arm64: Kconfig: drop unneeded dependency on OF_GPIO for ARCH_MVEBU + pxa/gpio + git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux tags/soc-pxa-gpio-for-v7.2 + zx/soc + https://gitlab.com/stefandoesinger/zx297520-kernel tags/zx29-plat-for-7.2 + +soc/dt + patch + arm64: dts: realtek: Add pinctrl support for RTD1625 + ARM: dts: ixp4xx: use phandle-based GPIOs in mi424wr + pxa1908/dt + https://codeberg.org/pxa1908-mainline/linux tags/pxa1908-dt-for-7.2 + renesas/dt + git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel tags/renesas-dts-for-v7.2-tag1 + contains renesas/fixes-1 + xz/dt + https://gitlab.com/stefandoesinger/zx297520-kernel tags/zx29-dts-for-7.2 + +soc/drivers + fsl/soc-driver + https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux tags/soc_fsl-7.1-2 + renesas/drivers + git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel tags/renesas-drivers-for-v7.2-tag1 + +soc/defconfig + patch + arm64: defconfig: Move entries to match savedefconfig + arm64: defconfig: Drop unused legacy netfilter options + arm64: defconfig: Drop default or selected drivers + arm64: defconfig: Drop unused Ethernet vendors + arm64: defconfig: Switch Ethernet drivers to modules + defconfig/pinctrl + git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl tags/v7.2-qcom-pinctrl-defconfigs + patch + ARM: multi_v7_defconfig: Move entries to match savedefconfig + ARM: configs: Drop redundant I2C_DESIGNWARE_PLATFORM + ARM: configs: Drop redundant SND_ATMEL_SOC + ARM: multi_v7_defconfig: Cleanup redundant options + ARM: multi_v7_defconfig: Correct QCOM_RPMH and QCOM_RPMHPD + arm64: defconfig: Enable PCI M.2 power sequencing driver + cix/defconfig + git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix tags/cix-defconfig-v7.2-rc1 + +soc/late + +arm/fixes + tee/fixes + git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee tags/tee-fixes-for-v7.1 + optee/fix + git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee tags/optee-fix-for-v7.1 + <no branch> (471c18323dfdfe7844e193b896a9267ae23a1026) + git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee tags/qcomtee-fix-for-v7.1 + qcom/fixes + https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux tags/qcom-drivers-fixes-for-7.1 + qcom/dt-fixes + https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux tags/qcom-arm64-fixes-for-7.1 + <no branch> (b73953af9bbd5c721c9d92b805a8aea8b0db74b1) + https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux tags/qcom-arm64-defconfig-fixes-for-7.1 + patch + ARM: dts: gemini: Fix partition offsets + imx/fixes +imx/fixes-2 + git://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux tags/imx-soc-fixes-for-v7.1 + diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index efe38eb253016..28fba538d5520 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -39,3 +39,4 @@ subdir-y += unisoc subdir-y += vt8500 subdir-y += xen subdir-y += xilinx +subdir-y += zte diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi index 9b54e3c01a345..3043ae7232dd0 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi @@ -195,19 +195,19 @@ pci-reset-hog { gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; output-high; line-name = "PCI reset"; }; pstn-relay-hog-1 { gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; output-low; line-name = "PSTN relay control 1"; }; pstn-relay-hog-2 { gpio-hog; - gpios = <12 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; output-low; line-name = "PSTN relay control 2"; }; diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index 2e19ebf9e2ba8..c3427dc7cf7dd 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -47,9 +47,117 @@ }; }; - ptm { - compatible = "arm,coresight-etm3x"; + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "atclk"; power-domains = <&pd_d4>; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + + in-ports { + /* replicator input port */ + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + etb@e6f81000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0xe6f81000 0 0x1000>; + clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@e6f83000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0xe6f83000 0 0x1000>; + clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + funnel { + compatible = "arm,coresight-static-funnel"; + + /* funnel output ports */ + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + }; + }; + + ptm@e6fbc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe6fbc000 0 0x1000>; + clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + cpu = <&cpu0>; + power-domains = <&pd_d4>; + + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; }; timer { @@ -512,7 +620,7 @@ clock-output-names = "main", "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", "m1", "m2", - "zx", "zs", "hp"; + "zx", "zs", "hp", "ztr", "zt"; }; /* Variable factor clocks (DIV6) */ diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi index d13ab86c3ab47..c7056b96ec0b7 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -18,7 +18,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0x0>; @@ -59,9 +59,117 @@ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; }; - ptm { - compatible = "arm,coresight-etm3x"; + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "atclk"; power-domains = <&pd_d4>; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + + in-ports { + /* replicator input port */ + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + etb@e6fa1000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0xe6fa1000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@e6fa3000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0xe6fa3000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + funnel { + compatible = "arm,coresight-static-funnel"; + + /* funnel output ports */ + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + }; + }; + + ptm@e6fbc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0xe6fbc000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + cpu = <&cpu0>; + power-domains = <&pd_d4>; + + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; }; ceu0: ceu@fe910000 { @@ -553,7 +661,7 @@ "usb24s", "i", "zg", "b", "m1", "hp", "hpp", "usbp", "s", "zb", "m3", - "cp"; + "cp", "ztr", "zt"; }; /* Variable factor clocks (DIV6) */ diff --git a/arch/arm/boot/dts/zte/Makefile b/arch/arm/boot/dts/zte/Makefile new file mode 100644 index 0000000000000..f052cfbd636cd --- /dev/null +++ b/arch/arm/boot/dts/zte/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_SOC_ZX297520V3) += \ + zx297520v3-dlink-dwr932m.dtb diff --git a/arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts b/arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts new file mode 100644 index 0000000000000..1700f46aba862 --- /dev/null +++ b/arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Stefan Dösinger <stefandoesinger@gmail.com> + */ + +/dts-v1/; + +#include "zx297520v3.dtsi" + +/ { + model = "D-Link DWR-932M"; + compatible = "dlink,dwr932m", "zte,zx297520v3"; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x04000000>; + }; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/zx297520v3.dtsi new file mode 100644 index 0000000000000..a16c30a164bb9 --- /dev/null +++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Stefan Dösinger <stefandoesinger@gmail.com> + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0>; + }; + }; + + /* Base bus clock and default for the UART. It will be replaced once a clock driver has + * been added. + */ + uartclk: uartclk-26000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + clock-frequency = <26000000>; + interrupt-parent = <&gic>; + /* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the + * arm timer at all. Since this is a single CPU system I don't think it + * really matters that the offset is random though. + */ + arm,cpu-registers-not-fw-configured; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + /* The GIC has a non-standard way of configuring ints between level-low/level + * high or rising edge/falling edge at 0xf2202070 and onwards. See AP_INT_MODE_BASE + * and AP_PPI_MODE_REG in the ZTE kernel, although the offsets in the kernel source + * seem wrong. + * + * Everything defaults to active-high/rising edge, but the timer is active-low. We + * currently rely on the boot loader to change timer IRQs to active-low for us for + * now. + */ + gic: interrupt-controller@f2000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf2000000 0x10000>, + <0xf2040000 0x20000>; + }; + + uart0: serial@131000 { + compatible = "arm,pl011", "arm,primecell"; + arm,primecell-periphid = <0x0018c011>; + reg = <0x00131000 0x1000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&uartclk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: serial@1408000 { + compatible = "arm,pl011", "arm,primecell"; + arm,primecell-periphid = <0x0018c011>; + reg = <0x01408000 0x1000>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&uartclk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@140d000 { + compatible = "arm,pl011", "arm,primecell"; + arm,primecell-periphid = <0x0018c011>; + reg = <0x0140d000 0x1000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&uartclk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 4f1153098b16f..e331242dece71 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -155,7 +155,6 @@ CONFIG_LOGO=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y -CONFIG_SND_ATMEL_SOC=y CONFIG_SND_AT91_SOC_SAM9G20_WM8731=y CONFIG_SND_ATMEL_SOC_WM8904=y CONFIG_SND_AT91_SOC_SAM9X5_WM8731=y diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig index 384aade1a48bb..dde9cff951d42 100644 --- a/arch/arm/configs/hisi_defconfig +++ b/arch/arm/configs/hisi_defconfig @@ -43,7 +43,6 @@ CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_PINCTRL_SINGLE=y diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig index 59b020e66a0b5..d0aea907124d5 100644 --- a/arch/arm/configs/multi_v5_defconfig +++ b/arch/arm/configs/multi_v5_defconfig @@ -186,7 +186,6 @@ CONFIG_BACKLIGHT_ATMEL_LCDC=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y -CONFIG_SND_ATMEL_SOC=y CONFIG_SND_AT91_SOC_SAM9G20_WM8731=m CONFIG_SND_ATMEL_SOC_WM8904=m CONFIG_SND_AT91_SOC_SAM9X5_WM8731=m diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index bcc9aabc12028..2891eeba90324 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -360,9 +360,9 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=5 CONFIG_SERIAL_8250_RUNTIME_UARTS=5 CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_ASPEED_VUART=m -CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_BCM2835AUX=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_EM=y @@ -387,7 +387,6 @@ CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SERIAL_VT8500=y CONFIG_SERIAL_VT8500_CONSOLE=y -CONFIG_SERIAL_BCM63XX=y CONFIG_SERIAL_BCM63XX_CONSOLE=y CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y @@ -420,7 +419,6 @@ CONFIG_I2C_BCM2835=y CONFIG_I2C_CADENCE=y CONFIG_I2C_DAVINCI=y CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_DIGICOLOR=m CONFIG_I2C_EMEV2=m CONFIG_I2C_IMX=y @@ -483,14 +481,6 @@ CONFIG_PINCTRL_PALMAS=y CONFIG_PINCTRL_STMFX=y CONFIG_PINCTRL_OWL=y CONFIG_PINCTRL_S500=y -CONFIG_PINCTRL_MSM=y -CONFIG_PINCTRL_APQ8064=y -CONFIG_PINCTRL_APQ8084=y -CONFIG_PINCTRL_IPQ8064=y -CONFIG_PINCTRL_MSM8660=y -CONFIG_PINCTRL_MSM8960=y -CONFIG_PINCTRL_MSM8X74=y -CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_QCOM_SSBI_PMIC=y CONFIG_PINCTRL_RZA2=y @@ -731,40 +721,8 @@ CONFIG_VIDEO_ADV7604_CEC=y CONFIG_VIDEO_ML86V7667=m CONFIG_IMX_IPUV3_CORE=m CONFIG_DRM=y -CONFIG_DRM_NOUVEAU=m -# CONFIG_DRM_NOUVEAU_CH7006 is not set -# CONFIG_DRM_NOUVEAU_SIL164 is not set -CONFIG_DRM_EXYNOS=m -CONFIG_DRM_EXYNOS_FIMD=y -CONFIG_DRM_EXYNOS_MIXER=y -CONFIG_DRM_EXYNOS_DPI=y -CONFIG_DRM_EXYNOS_DSI=y -CONFIG_DRM_EXYNOS_HDMI=y -CONFIG_DRM_ROCKCHIP=m -CONFIG_ROCKCHIP_ANALOGIX_DP=y -CONFIG_ROCKCHIP_DW_HDMI=y -CONFIG_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_ROCKCHIP_INNO_HDMI=y +CONFIG_DRM_ASPEED_GFX=m CONFIG_DRM_ATMEL_HLCDC=m -CONFIG_DRM_RCAR_DU=m -CONFIG_DRM_SUN4I=m -CONFIG_DRM_OMAP=m -CONFIG_OMAP5_DSS_HDMI=y -CONFIG_DRM_TILCDC=m -CONFIG_DRM_MSM=m -CONFIG_DRM_FSL_DCU=m -CONFIG_DRM_TEGRA=y -CONFIG_DRM_STM=m -CONFIG_DRM_STM_DSI=m -CONFIG_DRM_PANEL_LVDS=m -CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m -CONFIG_DRM_PANEL_RAYDIUM_RM68200=m -CONFIG_DRM_PANEL_SAMSUNG_LD9040=m -CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m -CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m -CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m -CONFIG_DRM_PANEL_EDP=y -CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_ITE_IT66121=m @@ -780,20 +738,52 @@ CONFIG_DRM_TI_TFP410=m CONFIG_DRM_TI_TPD12S015=m CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_I2C_ADV7511_AUDIO=y -CONFIG_DRM_STI=m +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_EXYNOS=m +CONFIG_DRM_EXYNOS_FIMD=y +CONFIG_DRM_EXYNOS_MIXER=y +CONFIG_DRM_EXYNOS_DPI=y +CONFIG_DRM_EXYNOS_DSI=y +CONFIG_DRM_EXYNOS_HDMI=y +CONFIG_DRM_FSL_DCU=m CONFIG_DRM_IMX=m CONFIG_DRM_IMX_PARALLEL_DISPLAY=m CONFIG_DRM_IMX_TVE=m CONFIG_DRM_IMX_LDB=m CONFIG_DRM_IMX_HDMI=m -CONFIG_DRM_V3D=m -CONFIG_DRM_VC4=m -CONFIG_DRM_ETNAVIV=m -CONFIG_DRM_MXSFB=m -CONFIG_DRM_PL111=m CONFIG_DRM_LIMA=m +CONFIG_DRM_MSM=m +CONFIG_DRM_MXSFB=m +CONFIG_DRM_NOUVEAU=m +# CONFIG_DRM_NOUVEAU_CH7006 is not set +# CONFIG_DRM_NOUVEAU_SIL164 is not set +CONFIG_DRM_OMAP=m +CONFIG_OMAP5_DSS_HDMI=y +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m +CONFIG_DRM_PANEL_RAYDIUM_RM68200=m +CONFIG_DRM_PANEL_SAMSUNG_LD9040=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m +CONFIG_DRM_PANEL_EDP=y +CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANFROST=m -CONFIG_DRM_ASPEED_GFX=m +CONFIG_DRM_PL111=m +CONFIG_DRM_RCAR_DU=m +CONFIG_DRM_ROCKCHIP=m +CONFIG_ROCKCHIP_ANALOGIX_DP=y +CONFIG_ROCKCHIP_DW_HDMI=y +CONFIG_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_ROCKCHIP_INNO_HDMI=y +CONFIG_DRM_STI=m +CONFIG_DRM_STM=m +CONFIG_DRM_STM_DSI=m +CONFIG_DRM_SUN4I=m +CONFIG_DRM_TEGRA=y +CONFIG_DRM_TILCDC=m +CONFIG_DRM_V3D=m +CONFIG_DRM_VC4=m CONFIG_FB=y CONFIG_FB_EFI=y CONFIG_FB_WM8505=y @@ -811,27 +801,22 @@ CONFIG_SND_HDA_INPUT_BEEP=y CONFIG_SND_HDA_PATCH_LOADER=y CONFIG_SND_HDA_TEGRA=m CONFIG_SND_HDA_CODEC_REALTEK=m -CONFIG_SND_HDA_CODEC_REALTEK_LIB=m -CONFIG_SND_HDA_CODEC_ALC269=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_HDMI_GENERIC=m CONFIG_SND_HDA_CODEC_HDMI_NVIDIA=m CONFIG_SND_HDA_CODEC_HDMI_TEGRA=m CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=m -CONFIG_SND_ATMEL_SOC=m CONFIG_SND_ATMEL_SOC_WM8904=m CONFIG_SND_ATMEL_SOC_PDMIC=m CONFIG_SND_ATMEL_SOC_I2S=m CONFIG_SND_BCM2835_SOC_I2S=m CONFIG_SND_IMX_SOC=m CONFIG_SND_SOC_FSL_ASOC_CARD=m -CONFIG_SND_PXA_SOC_SSP=m CONFIG_SND_MMP_SOC_SSPA=m CONFIG_SND_PXA910_SOC=m CONFIG_SND_SOC_QCOM=m CONFIG_SND_SOC_APQ8016_SBC=m -CONFIG_SND_SOC_ROCKCHIP=m CONFIG_SND_SOC_SH4_FSI=m CONFIG_SND_SOC_RCAR=m CONFIG_SND_SOC_ROCKCHIP_SPDIF=m @@ -873,7 +858,6 @@ CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_STI_SAS=m -CONFIG_SND_SOC_TLV320AIC32X4=m CONFIG_SND_SOC_TLV320AIC32X4_I2C=m CONFIG_SND_SOC_TLV320AIC3X_I2C=m CONFIG_SND_SOC_WM8960=m @@ -933,7 +917,6 @@ CONFIG_KEYSTONE_USB_PHY=m CONFIG_NOP_USB_XCEIV=y CONFIG_AM335X_PHY_USB=m CONFIG_TWL6030_USB=m -CONFIG_USB_GPIO_VBUS=y CONFIG_USB_ISP1301=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y @@ -1155,7 +1138,7 @@ CONFIG_QCOM_COMMAND_DB=m CONFIG_QCOM_GSBI=y CONFIG_QCOM_OCMEM=m CONFIG_QCOM_RMTFS_MEM=m -CONFIG_QCOM_RPMH=y +CONFIG_QCOM_RPMH=m CONFIG_QCOM_SMEM=y CONFIG_QCOM_SMD_RPM=y CONFIG_QCOM_SMP2P=y @@ -1170,7 +1153,7 @@ CONFIG_KEYSTONE_NAVIGATOR_DMA=y CONFIG_TI_PRUSS=m CONFIG_RASPBERRYPI_POWER=y CONFIG_QCOM_CPR=y -CONFIG_QCOM_RPMHPD=y +CONFIG_QCOM_RPMHPD=m CONFIG_QCOM_RPMPD=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_TI_SCI_PM_DOMAINS=y diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index c51ae373ca888..6bbf40d073eeb 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig @@ -278,7 +278,6 @@ CONFIG_I2C_CHARDEV=m CONFIG_I2C_MUX_PCA954x=m CONFIG_I2C_MUX_PINCTRL=m CONFIG_I2C_DESIGNWARE_CORE=m -CONFIG_I2C_DESIGNWARE_PLATFORM=m CONFIG_I2C_GPIO=y CONFIG_I2C_PXA_SLAVE=y CONFIG_I2C_XILINX=m @@ -404,7 +403,6 @@ CONFIG_SND_DEBUG=y CONFIG_SND_SEQUENCER=m CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=m -CONFIG_SND_ATMEL_SOC=m CONFIG_SND_PXA2XX_SOC=m CONFIG_SND_PXA_SOC_SSP=m CONFIG_SND_PXA2XX_SOC_SPITZ=m diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index 29a1dea500f08..03309b89ea4cf 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -123,22 +123,7 @@ CONFIG_I2C_QUP=y CONFIG_SPI=y CONFIG_SPI_QUP=y CONFIG_SPMI=y -CONFIG_PINCTRL_MSM=y -CONFIG_PINCTRL_APQ8064=y -CONFIG_PINCTRL_APQ8084=y -CONFIG_PINCTRL_IPQ4019=y -CONFIG_PINCTRL_IPQ8064=y -CONFIG_PINCTRL_MSM8226=y -CONFIG_PINCTRL_MSM8660=y -CONFIG_PINCTRL_MSM8960=y -CONFIG_PINCTRL_MDM9607=y -CONFIG_PINCTRL_MDM9615=y -CONFIG_PINCTRL_MSM8X74=y -CONFIG_PINCTRL_MSM8909=y -CONFIG_PINCTRL_MSM8916=y CONFIG_GPIOLIB=y -CONFIG_PINCTRL_SDX55=y -CONFIG_PINCTRL_SDX65=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_QCOM_SSBI_PMIC=y CONFIG_GPIO_SYSFS=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 2cad045e1d8d7..bd7f0b5f7d660 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -168,7 +168,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y -CONFIG_SND_ATMEL_SOC=y CONFIG_SND_ATMEL_SOC_WM8904=y CONFIG_SND_ATMEL_SOC_CLASSD=y CONFIG_SND_ATMEL_SOC_PDMIC=y diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index e52f671ccec4e..47abc56c40f59 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -159,7 +159,6 @@ CONFIG_BACKLIGHT_PWM=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y -CONFIG_SND_ATMEL_SOC=y CONFIG_SND_SOC_MIKROE_PROTO=m CONFIG_SND_MCHP_SOC_I2S_MCC=y CONFIG_SND_MCHP_SOC_SPDIFTX=y diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig index f2e42846b1169..19a8e30a7b226 100644 --- a/arch/arm/configs/socfpga_defconfig +++ b/arch/arm/configs/socfpga_defconfig @@ -84,7 +84,6 @@ CONFIG_SERIAL_8250_DW=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y CONFIG_SPI_CADENCE_QUADSPI=y CONFIG_SPI_DESIGNWARE=y diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig index 8b19af1ea67c7..6712ae741c196 100644 --- a/arch/arm/configs/spear13xx_defconfig +++ b/arch/arm/configs/spear13xx_defconfig @@ -63,7 +63,6 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_RAW_DRIVER=y CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_GPIO_SYSFS=y diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig index b4e4b96a98afa..b96baa63fd582 100644 --- a/arch/arm/configs/spear3xx_defconfig +++ b/arch/arm/configs/spear3xx_defconfig @@ -43,7 +43,6 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_RAW_DRIVER=y CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_GPIO_SYSFS=y diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig index 7083b1bd85739..dba3bf3fa19aa 100644 --- a/arch/arm/configs/spear6xx_defconfig +++ b/arch/arm/configs/spear6xx_defconfig @@ -34,7 +34,6 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_GPIO_PL061=y diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index 9de3bbc09c3a0..670e6587827e4 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -6,6 +6,7 @@ menuconfig ARCH_MV78XX0 depends on ATAGS select CPU_FEROCEON select GPIOLIB + select GPIOLIB_LEGACY select MVEBU_MBUS select FORCE_PCI select PLAT_ORION_LEGACY diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index ee449ca032d21..cef19bea61641 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -5,6 +5,7 @@ menuconfig ARCH_ORION5X depends on CPU_LITTLE_ENDIAN select CPU_FEROCEON select GPIOLIB + select GPIOLIB_LEGACY select MVEBU_MBUS select FORCE_PCI select PCI_QUIRKS diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 10e472f4fa434..66e26990e2c8d 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -10,6 +10,7 @@ menuconfig ARCH_PXA select CPU_XSCALE if !CPU_XSC3 select GPIO_PXA select GPIOLIB + select GPIOLIB_LEGACY select PLAT_PXA help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 70509a5998142..a4e878be004a0 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -240,6 +240,9 @@ static int __init pxa25x_init(void) if (!of_have_populated_dt()) { software_node_register(&pxa2xx_gpiochip_node); + pxa25x_device_gpio.dev.fwnode = software_node_fwnode( + &pxa2xx_gpiochip_node); + pxa2xx_set_dmac_info(&pxa25x_dma_pdata); ret = platform_add_devices(pxa25x_devices, ARRAY_SIZE(pxa25x_devices)); diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index ff63619790383..49c677f2dac15 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -342,6 +342,9 @@ static int __init pxa27x_init(void) if (!of_have_populated_dt()) { software_node_register(&pxa2xx_gpiochip_node); + pxa27x_device_gpio.dev.fwnode = software_node_fwnode( + &pxa2xx_gpiochip_node); + pxa2xx_set_dmac_info(&pxa27x_dma_pdata); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index c0b1f7e6be874..5091b601c4e1b 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -165,7 +165,7 @@ static struct scoop_config spitz_scoop_1_setup = { .gpio_base = SPITZ_SCP_GPIO_BASE, }; -struct platform_device spitz_scoop_1_device = { +static struct platform_device spitz_scoop_1_device = { .name = "sharp-scoop", .id = 0, .dev = { @@ -192,7 +192,7 @@ static struct scoop_config spitz_scoop_2_setup = { .gpio_base = SPITZ_SCP2_GPIO_BASE, }; -struct platform_device spitz_scoop_2_device = { +static struct platform_device spitz_scoop_2_device = { .name = "sharp-scoop", .id = 1, .dev = { @@ -204,11 +204,15 @@ struct platform_device spitz_scoop_2_device = { static void __init spitz_scoop_init(void) { + spitz_scoop_1_device.dev.fwnode = software_node_fwnode(&spitz_scoop_1_gpiochip_node); platform_device_register(&spitz_scoop_1_device); /* Akita doesn't have the second SCOOP chip */ - if (!machine_is_akita()) + if (!machine_is_akita()) { + spitz_scoop_2_device.dev.fwnode = software_node_fwnode( + &spitz_scoop_2_gpiochip_node); platform_device_register(&spitz_scoop_2_device); + } } /* Power control is shared with between one of the CF slots and SD */ @@ -988,6 +992,7 @@ static struct i2c_board_info spitz_i2c_devs[] = { .type = "max7310", .addr = 0x18, .platform_data = &akita_pca953x_pdata, + .swnode = &akita_max7310_gpiochip_node, }, }; diff --git a/arch/arm/mach-s3c/Kconfig.s3c64xx b/arch/arm/mach-s3c/Kconfig.s3c64xx index 8f40af063ad6f..3f97fba8e4f52 100644 --- a/arch/arm/mach-s3c/Kconfig.s3c64xx +++ b/arch/arm/mach-s3c/Kconfig.s3c64xx @@ -101,6 +101,7 @@ config MACH_WLF_CRAGG_6410 depends on ATAGS depends on I2C=y select CPU_S3C6410 + select GPIOLIB_LEGACY select LEDS_GPIO_REGISTER select S3C64XX_DEV_SPI0 select S3C64XX_SETUP_FB_24BPP diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index 0fb4c24cfad54..e23700e0d6c88 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig @@ -13,6 +13,7 @@ menuconfig ARCH_SA1100 select CPU_FREQ select CPU_SA1100 select GPIOLIB + select GPIOLIB_LEGACY select IRQ_DOMAIN select ISA select NEED_MACH_MEMORY_H diff --git a/arch/arm/mach-zte/Kconfig b/arch/arm/mach-zte/Kconfig new file mode 100644 index 0000000000000..d3b404ca488d4 --- /dev/null +++ b/arch/arm/mach-zte/Kconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-only +menuconfig ARCH_ZTE + bool "ZTE zx family" + depends on ARCH_MULTI_V7 + help + Support for ZTE zx-based family of processors. + +if ARCH_ZTE + +config SOC_ZX297520V3 + bool "zx297520v3 SoC" + default y + select ARM_GIC_V3 + # This board does not have PSCI firmware, but ARM_GIC_V3 depends on + # ARM_PSCI_FW being enabled. + select ARM_PSCI_FW + select ARM_AMBA + select HAVE_ARM_ARCH_TIMER + select PM_GENERIC_DOMAINS if PM + help + Support for ZTE zx297520v3 SoC. It is a single core SoC used in cheap + LTE to WiFi routers. These devices can be identified by the occurrence + of the string "zx297520v3" in the boot output and /proc/cpuinfo of + their stock firmware. + + Please read Documentation/arch/arm/zte/zx297520v3.rst on how to boot + the kernel. + +endif diff --git a/arch/arm/mach-zte/Makefile b/arch/arm/mach-zte/Makefile new file mode 100644 index 0000000000000..1bfe4fddd6af7 --- /dev/null +++ b/arch/arm/mach-zte/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_SOC_ZX297520V3) += zx297520v3.o diff --git a/arch/arm/mach-zte/zx297520v3.c b/arch/arm/mach-zte/zx297520v3.c new file mode 100644 index 0000000000000..06f71348459e2 --- /dev/null +++ b/arch/arm/mach-zte/zx297520v3.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2026 Stefan Dösinger + */ + +#include <asm/mach/arch.h> +#include <linux/init.h> + +static const char *const zx297520v3_dt_compat[] __initconst = { + "zte,zx297520v3", + NULL, +}; + +DT_MACHINE_START(ZX, "ZTE zx297520v3 (Device Tree)") + .dt_compat = zx297520v3_dt_compat, +MACHINE_END diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 72c812e76b0b1..dc995a7321174 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -243,7 +243,6 @@ config ARCH_MVEBU select MVEBU_ODMI select MVEBU_PIC select MVEBU_SEI - select OF_GPIO select PINCTRL select PINCTRL_ARMADA_37XX select PINCTRL_ARMADA_AP806 diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts index b2ce5edd9c6ac..6ec899c427e14 100644 --- a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts +++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts @@ -23,7 +23,7 @@ fb0: framebuffer@17177000 { compatible = "simple-framebuffer"; - reg = <0 0x17177000 0 (480 * 800 * 4)>; + memory-region = <&fb_mem>; power-domains = <&apmu PXA1908_POWER_DOMAIN_DSI>; width = <480>; height = <800>; @@ -48,8 +48,9 @@ reg = <0 0 0 0x1000000>; }; - framebuffer@17000000 { - reg = <0 0x17000000 0 0x1800000>; + /* The "active buffer" is at 0x17000000 + (size of one buffer). */ + fb_mem: framebuffer@17177000 { + reg = <0 0x17177000 0 (480 * 800 * 4)>; no-map; }; }; @@ -460,7 +461,7 @@ regulators { ldo2: ldo2 { - regulator-min-microvolt = <1900000>; + regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3100000>; }; @@ -523,6 +524,8 @@ pinctrl-1 = <&sdh1_fast_pins_0 &sdh1_fast_pins_1 &sdh1_pins_2>; bus-width = <4>; non-removable; + keep-power-in-suspend; + wakeup-source; }; &pwm3 { diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi b/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi index 5778bfdb85675..91022b62a39b1 100644 --- a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi +++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi @@ -55,8 +55,11 @@ }; psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci-0.2", "arm,psci"; method = "smc"; + + cpu_off = <0x85000001>; + cpu_on = <0x85000002>; }; reserved-memory { diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi index ae006ce244205..8d4293cd4c036 100644 --- a/arch/arm64/boot/dts/realtek/kent.dtsi +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -150,6 +150,26 @@ reg-shift = <2>; status = "disabled"; }; + + iso_pinctrl: pinctrl@4e000 { + compatible = "realtek,rtd1625-iso-pinctrl"; + reg = <0x4e000 0x1a4>; + }; + + main2_pinctrl: pinctrl@4f200 { + compatible = "realtek,rtd1625-main2-pinctrl"; + reg = <0x4f200 0x50>; + }; + + isom_pinctrl: pinctrl@146200 { + compatible = "realtek,rtd1625-isom-pinctrl"; + reg = <0x146200 0x34>; + }; + + ve4_pinctrl: pinctrl@14e000 { + compatible = "realtek,rtd1625-ve4-pinctrl"; + reg = <0x14e000 0x84>; + }; }; gic: interrupt-controller@ff100000 { diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index aaedb1fb51aed..ba564aa098661 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -186,23 +186,6 @@ regulator-always-on; }; - rsnd_ak4613: sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "rsnd-ak4613"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4613>; - }; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - }; - vbus0_usb2: regulator-vbus0-usb2 { compatible = "regulator-fixed"; @@ -260,6 +243,23 @@ states = <3300000 1>, <1800000 0>; }; + rsnd_ak4613: sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "rsnd-ak4613"; + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4613>; + }; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + }; + vga { compatible = "vga-connector"; diff --git a/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi b/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi index 2edb5cb3407b4..792a4aa8f4a9d 100644 --- a/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi +++ b/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi @@ -208,11 +208,11 @@ avb0_phy: ethernet-phy@0 { compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts index d5543f26c4720..0d5c754a7f0ec 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts @@ -35,3 +35,7 @@ clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts index 9ebb47b6bf2dc..115cc47bb0724 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts @@ -35,3 +35,7 @@ clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts index 4bfeb1df0488d..c3282593346bc 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts @@ -36,3 +36,7 @@ clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts index c7f14177f7b95..b35de49406a01 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts @@ -40,3 +40,7 @@ clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts index 70cf926667a6e..0c0806cec6989 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts @@ -40,3 +40,7 @@ clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 593c66b27ad12..ded4f1f11d605 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -604,6 +604,7 @@ resets = <&cpg R9A07G043_GPIO_RSTN>, <&cpg R9A07G043_GPIO_PORT_RESETN>, <&cpg R9A07G043_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; dmac: dma-controller@11820000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 29273da819951..cb0c9550aa033 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1017,6 +1017,7 @@ resets = <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; irqc: interrupt-controller@110a0000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 0dee48c4f1e44..7a3e5b6a685f5 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1025,6 +1025,7 @@ resets = <&cpg R9A07G054_GPIO_RSTN>, <&cpg R9A07G054_GPIO_PORT_RESETN>, <&cpg R9A07G054_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; irqc: interrupt-controller@110a0000 { diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 997e6cf0bb824..3a69bb246babd 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -533,6 +533,7 @@ resets = <&cpg R9A08G045_GPIO_RSTN>, <&cpg R9A08G045_GPIO_PORT_RESETN>, <&cpg R9A08G045_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; irqc: interrupt-controller@11050000 { diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 28b0c75587483..02a3029c058e2 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -14,6 +14,42 @@ #size-cells = <2>; interrupt-parent = <&gic>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +60,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC0>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -32,6 +70,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC1>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -40,6 +80,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -48,6 +90,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC3>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { @@ -160,10 +204,111 @@ }; pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a08g046-pinctrl"; reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; - /* placeholder */ + gpio-ranges = <&pinctrl 0 0 232>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu>; + clocks = <&cpg CPG_MOD R9A08G046_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_GPIO_RSTN>, + <&cpg R9A08G046_GPIO_PORT_RESETN>, + <&cpg R9A08G046_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; + renesas,clonech = <&sysc 0xe2c>; + }; + + icu: interrupt-controller@11050000 { + compatible = "renesas,r9a08g046-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x11050000 0 0x10000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err", "ec7tie1-0", "ec7tie2-0", "ec7tiovf-0", + "ovfunf0", "ovfunf1", "ovfunf2", "ovfunf3", + "ovfunf4", "ovfunf5", "ovfunf6", "ovfunf7"; + clocks = <&cpg CPG_MOD R9A08G046_IA55_CLK>, + <&cpg CPG_MOD R9A08G046_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_IA55_RESETN>; }; sdhi1: mmc@11c10000 { @@ -171,6 +316,240 @@ /* placeholder */ }; + eth0: ethernet@11c30000 { + compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3", "ptp-pps-0", + "ptp-pps-1", "ptp-pps-2", "ptp-pps-3"; + clocks = <&cpg CPG_MOD R9A08G046_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_PTP_REF_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RMII_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I_RMII>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I_RMII>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180", + "rmii", "rmii_tx", "rmii_rx"; + resets = <&cpg R9A08G046_ETH0_ARESET_N>; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup0>; + snps,mtl-tx-config = <&mtl_tx_setup0>; + snps,txpbl = <32>; + snps,rxpbl = <32>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup0: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + }; + + mtl_tx_setup0: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,weight = <0x14>; + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,weight = <0x18>; + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + }; + }; + + eth1: ethernet@11c40000 { + compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a"; + reg = <0 0x11c40000 0 0x10000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 105 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3", "ptp-pps-0", + "ptp-pps-1", "ptp-pps-2", "ptp-pps-3"; + clocks = <&cpg CPG_MOD R9A08G046_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_CHI>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_PTP_REF_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RMII_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I_RMII>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I_RMII>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180", + "rmii", "rmii_tx", "rmii_rx"; + resets = <&cpg R9A08G046_ETH1_ARESET_N>; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,txpbl = <32>; + snps,rxpbl = <32>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,weight = <0x14>; + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,weight = <0x18>; + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + }; + }; + pcie: pcie@11e40000 { reg = <0 0x11e40000 0 0x10000>; ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; @@ -198,6 +577,27 @@ interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a08g046-wdt", "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A08G046_WDT0_PCLK>, + <&cpg CPG_MOD R9A08G046_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A08G046_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <16 8 4 0 0 0 0>; }; timer { diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index 86db86335d5e0..0ae052238b3b5 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -14,6 +14,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h> #include "r9a08g046l48.dtsi" #include "rzg3l-smarc-som.dtsi" #include "renesas-smarc2.dtsi" @@ -35,3 +36,15 @@ /delete-node/ key-2; /delete-node/ key-3; }; + +&pinctrl { + scif0_pins: scif0 { + pins = "SCIF0_TXD", "SCIF0_RXD"; + power-source = <1800>; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 95a4e30a064d1..4267b10937f3f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -265,6 +265,7 @@ interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; + reset-names = "main", "error"; }; cpg: clock-controller@10420000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 7ccddd6a4a9ad..dc5b116679c0c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -288,6 +288,7 @@ gpio-ranges = <&pinctrl 0 0 96>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; + reset-names = "main", "error"; }; cpg: clock-controller@10420000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 6f6fe5f36bef3..1e94366bb7eee 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -270,6 +270,7 @@ interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; + reset-names = "main", "error"; }; cpg: clock-controller@10420000 { diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index ab4950671c7c8..b28e59a652599 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -8,6 +8,11 @@ / { compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046"; + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + }; + memory@48000000 { device_type = "memory"; /* First 128MiB is reserved for secure area. */ @@ -15,6 +20,133 @@ }; }; +ð0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +ð0_rxc_rx_clk { + clock-frequency = <125000000>; +}; + +ð1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +ð1_rxc_rx_clk { + clock-frequency = <125000000>; +}; + &extal_clk { clock-frequency = <24000000>; }; + +&mdio0 { + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640"; + reg = <7>; + interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-psec = <1400>; + txc-skew-psec = <1400>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +&mdio1 { + phy1: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640"; + reg = <7>; + interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-psec = <1400>; + txc-skew-psec = <1400>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +&pinctrl { + eth0_pins: eth0 { + txc { + pinmux = <RZG3L_PORT_PINMUX(B, 1, 1)>; /* ETH0_TXC_REF_CLK */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + ctrl { + pinmux = <RZG3L_PORT_PINMUX(A, 0, 1)>, /* MDIO */ + <RZG3L_PORT_PINMUX(A, 1, 1)>, /* MDC */ + <RZG3L_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */ + <RZG3L_PORT_PINMUX(A, 3, 1)>, /* TX_CTL */ + <RZG3L_PORT_PINMUX(B, 0, 1)>, /* RXC */ + <RZG3L_PORT_PINMUX(B, 2, 1)>, /* TXD0 */ + <RZG3L_PORT_PINMUX(B, 3, 1)>, /* TXD1 */ + <RZG3L_PORT_PINMUX(B, 4, 1)>, /* TXD2 */ + <RZG3L_PORT_PINMUX(B, 5, 1)>, /* TXD3 */ + <RZG3L_PORT_PINMUX(B, 6, 1)>, /* RXD0 */ + <RZG3L_PORT_PINMUX(B, 7, 1)>, /* RXD1 */ + <RZG3L_PORT_PINMUX(C, 0, 1)>, /* RXD2 */ + <RZG3L_PORT_PINMUX(C, 1, 1)>, /* RXD3 */ + <RZG3L_PORT_PINMUX(C, 2, 15)>; /* PHY_INTR */ + power-source = <1800>; + }; + }; + + eth1_pins: eth1 { + txc { + pinmux = <RZG3L_PORT_PINMUX(E, 1, 1)>; /* ETH1_TXC_REF_CLK */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + ctrl { + pinmux = <RZG3L_PORT_PINMUX(D, 0, 1)>, /* MDIO */ + <RZG3L_PORT_PINMUX(D, 1, 1)>, /* MDC */ + <RZG3L_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */ + <RZG3L_PORT_PINMUX(D, 3, 1)>, /* TX_CTL */ + <RZG3L_PORT_PINMUX(E, 0, 1)>, /* RXC */ + <RZG3L_PORT_PINMUX(E, 2, 1)>, /* TXD0 */ + <RZG3L_PORT_PINMUX(E, 3, 1)>, /* TXD1 */ + <RZG3L_PORT_PINMUX(E, 4, 1)>, /* TXD2 */ + <RZG3L_PORT_PINMUX(E, 5, 1)>, /* TXD3 */ + <RZG3L_PORT_PINMUX(E, 6, 1)>, /* RXD0 */ + <RZG3L_PORT_PINMUX(E, 7, 1)>, /* RXD1 */ + <RZG3L_PORT_PINMUX(F, 0, 1)>, /* RXD2 */ + <RZG3L_PORT_PINMUX(F, 1, 1)>, /* RXD3 */ + <RZG3L_PORT_PINMUX(F, 2, 15)>; /* PHY_INTR */ + power-source = <1800>; + }; + }; +}; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index e505161caa675..0b29bf9564eb1 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -211,19 +211,6 @@ regulator-always-on; }; - sound_card: sound { - compatible = "audio-graph-card"; - - label = "rcar-sound"; - - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ -#ifdef SOC_HAS_HDMI1 - &rsnd_port2 /* HDMI1 */ -#endif - >; - }; - vbus0_usb2: regulator-vbus0-usb2 { compatible = "regulator-fixed"; @@ -281,6 +268,19 @@ states = <3300000 1>, <1800000 0>; }; + sound_card: sound { + compatible = "audio-graph-card"; + + label = "rcar-sound"; + + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ +#ifdef SOC_HAS_HDMI1 + &rsnd_port2 /* HDMI1 */ +#endif + >; + }; + vga { compatible = "vga-connector"; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 96ce783f24e72..340313d48e0f8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -50,7 +50,6 @@ CONFIG_ARCH_BLAIZE=y CONFIG_ARCH_BST=y CONFIG_ARCH_CIX=y CONFIG_ARCH_EXYNOS=y -CONFIG_ARCH_SPARX5=y CONFIG_ARCH_K3=y CONFIG_ARCH_LG1K=y CONFIG_ARCH_HISI=y @@ -58,6 +57,7 @@ CONFIG_ARCH_KEEMBAY=y CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_MESON=y CONFIG_ARCH_MICROCHIP=y +CONFIG_ARCH_SPARX5=y CONFIG_ARCH_MVEBU=y CONFIG_ARCH_NXP=y CONFIG_ARCH_LAYERSCAPE=y @@ -99,7 +99,6 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m CONFIG_CPUFREQ_DT=y -CONFIG_ACPI_CPPC_CPUFREQ=m CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m CONFIG_ARM_APPLE_SOC_CPUFREQ=m CONFIG_ARM_ARMADA_37XX_CPUFREQ=y @@ -112,6 +111,7 @@ CONFIG_ARM_RASPBERRYPI_CPUFREQ=m CONFIG_ARM_SCMI_CPUFREQ=y CONFIG_ARM_TEGRA186_CPUFREQ=y CONFIG_QORIQ_CPUFREQ=y +CONFIG_ACPI_CPPC_CPUFREQ=m CONFIG_ACPI=y CONFIG_ACPI_HOTPLUG_MEMORY=y CONFIG_ACPI_HMAT=y @@ -126,6 +126,7 @@ CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_IOSCHED_BFQ=y +CONFIG_BLK_INLINE_ENCRYPTION=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_COMPAT_BRK is not set CONFIG_MEMORY_HOTPLUG=y @@ -154,17 +155,7 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_IPVS=m CONFIG_IP_VS=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_MANGLE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_BRIDGE=m CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_NET_DSA=m @@ -182,8 +173,8 @@ CONFIG_NET_CLS_FLOWER=m CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_GACT=m CONFIG_NET_ACT_MIRRED=m -CONFIG_HSR=m CONFIG_NET_ACT_GATE=m +CONFIG_HSR=m CONFIG_QRTR_SMD=m CONFIG_QRTR_TUN=m CONFIG_CAN=m @@ -208,8 +199,8 @@ CONFIG_MAC80211=m CONFIG_MAC80211_LEDS=y CONFIG_RFKILL=m CONFIG_RFKILL_GPIO=m -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y +CONFIG_NET_9P=m +CONFIG_NET_9P_VIRTIO=m CONFIG_NFC=m CONFIG_NFC_NCI=m CONFIG_NFC_NXP_NCI=m @@ -241,7 +232,9 @@ CONFIG_PCIE_XILINX=y CONFIG_PCIE_XILINX_DMA_PL=y CONFIG_PCIE_XILINX_NWL=y CONFIG_PCIE_XILINX_CPM=y +CONFIG_PCI_SKY1_HOST=m CONFIG_PCI_J721E_HOST=m +CONFIG_PCI_SKY1_HOST=m CONFIG_PCI_IMX6_HOST=y CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_HISI=y @@ -265,6 +258,7 @@ CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_FW_LOADER_USER_HELPER=y CONFIG_HISILICON_LPC=y +CONFIG_IMX_AIPSTZ=m CONFIG_TEGRA_ACONNECT=m CONFIG_MHI_BUS_PCI_GENERIC=m CONFIG_ARM_SCMI_PROTOCOL=y @@ -277,7 +271,6 @@ CONFIG_GOOGLE_FIRMWARE=y CONFIG_GOOGLE_CBMEM=m CONFIG_GOOGLE_COREBOOT_TABLE=m CONFIG_EFI_CAPSULE_LOADER=y -CONFIG_IMX_AIPSTZ=m CONFIG_IMX_SCU=y CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE=y CONFIG_QCOM_QSEECOM=y @@ -304,11 +297,12 @@ CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_BRCMNAND=m CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_NAND_QCOM=y -CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=y CONFIG_MTD_UBI=m CONFIG_MTD_HYPERBUS=m CONFIG_HBMC_AM654=m +CONFIG_OF_OVERLAY=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m CONFIG_VIRTIO_BLK=y @@ -322,6 +316,7 @@ CONFIG_XILINX_SDFEC=m CONFIG_EEPROM_AT24=m CONFIG_EEPROM_AT25=m CONFIG_UACCE=m +CONFIG_MISC_RP1=m # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y CONFIG_SCSI_SAS_ATA=y @@ -356,58 +351,110 @@ CONFIG_VIRTIO_NET=y CONFIG_MHI_NET=m CONFIG_NET_DSA_BCM_SF2=m CONFIG_NET_DSA_MSCC_FELIX=m +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ACTIONS is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALLWINNER is not set CONFIG_ENA_ETHERNET=m -CONFIG_AMD_XGBE=y +CONFIG_AMD_XGBE=m CONFIG_NET_XGENE=y +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ASIX is not set CONFIG_ATL1C=m +CONFIG_BCM4908_ENET=m CONFIG_BCMGENET=m CONFIG_BNX2X=m +CONFIG_BGMAC_PLATFORM=m CONFIG_SYSTEMPORT=m -CONFIG_MACB=y -CONFIG_THUNDER_NIC_PF=y -CONFIG_FEC=y -CONFIG_FSL_FMAN=y -CONFIG_FSL_DPAA_ETH=y -CONFIG_FSL_DPAA2_ETH=y -CONFIG_FSL_ENETC=y +CONFIG_BCMASP=m +CONFIG_MACB=m +CONFIG_THUNDER_NIC_PF=m +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_FEC=m +CONFIG_FSL_FMAN=m +CONFIG_FSL_DPAA_ETH=m +CONFIG_FSL_DPAA2_ETH=m +CONFIG_FSL_ENETC=m CONFIG_NXP_ENETC4=m -CONFIG_FSL_ENETC_VF=y +CONFIG_FSL_ENETC_VF=m CONFIG_FSL_ENETC_QOS=y CONFIG_NXP_NETC_BLK_CTRL=m -CONFIG_HIX5HD2_GMAC=y -CONFIG_HNS_DSAF=y -CONFIG_HNS_ENET=y -CONFIG_HNS3=y -CONFIG_HNS3_HCLGE=y -CONFIG_HNS3_ENET=y -CONFIG_E1000=y -CONFIG_E1000E=y -CONFIG_IGB=y -CONFIG_IGBVF=y -CONFIG_MVNETA=y -CONFIG_MVPP2=y -CONFIG_SKY2=y +# CONFIG_NET_VENDOR_FUNGIBLE is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +CONFIG_HIX5HD2_GMAC=m +CONFIG_HNS_DSAF=m +CONFIG_HNS_ENET=m +CONFIG_HNS3=m +# CONFIG_NET_VENDOR_HUAWEI is not set +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGBVF=m +# CONFIG_NET_VENDOR_ADI is not set +# CONFIG_NET_VENDOR_LITEX is not set +CONFIG_MVNETA=m +CONFIG_MVPP2=m +CONFIG_SKY2=m CONFIG_NET_VENDOR_MEDIATEK=y CONFIG_NET_MEDIATEK_STAR_EMAC=m CONFIG_MLX4_EN=m CONFIG_MLX5_CORE=m CONFIG_MLX5_CORE_EN=y +# CONFIG_NET_VENDOR_META is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_MUCSE is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_BROCADE is not set CONFIG_QCOM_EMAC=m CONFIG_RMNET=m +# CONFIG_NET_VENDOR_RDC is not set CONFIG_R8169=m -CONFIG_SH_ETH=y -CONFIG_RAVB=y -CONFIG_RENESAS_ETHER_SWITCH=y -CONFIG_RTSN=y -CONFIG_SMC91X=y -CONFIG_SMSC911X=y -CONFIG_SNI_AVE=y -CONFIG_SNI_NETSEC=y +CONFIG_SH_ETH=m +CONFIG_RAVB=m +CONFIG_RENESAS_ETHER_SWITCH=m +CONFIG_RTSN=m +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +CONFIG_SMC91X=m +CONFIG_SMSC911X=m +CONFIG_SNI_AVE=m +CONFIG_SNI_NETSEC=m CONFIG_STMMAC_ETH=m CONFIG_DWMAC_MEDIATEK=m CONFIG_DWMAC_TEGRA=m -CONFIG_TI_K3_AM65_CPSW_NUSS=y +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +CONFIG_TI_K3_AM65_CPSW_NUSS=m CONFIG_TI_ICSSG_PRUETH=m +# CONFIG_NET_VENDOR_VERTEXCOM is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WANGXUN is not set +# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_XILINX_AXI_EMAC=m CONFIG_QCOM_IPA=m CONFIG_MESON_GXL_PHY=m @@ -424,8 +471,8 @@ CONFIG_REALTEK_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_DP83867_PHY=y CONFIG_DP83869_PHY=m -CONFIG_DP83TG720_PHY=m CONFIG_DP83TD510_PHY=y +CONFIG_DP83TG720_PHY=m CONFIG_VITESSE_PHY=y CONFIG_XILINX_GMII2RGMII=m CONFIG_CAN_FLEXCAN=m @@ -435,7 +482,7 @@ CONFIG_CAN_M_CAN_PLATFORM=m CONFIG_CAN_RCAR=m CONFIG_CAN_RCAR_CANFD=m CONFIG_CAN_MCP251XFD=m -CONFIG_MDIO_GPIO=y +CONFIG_MDIO_GPIO=m CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_USB_PEGASUS=m @@ -557,6 +604,7 @@ CONFIG_TCG_TIS_SPI=m CONFIG_TCG_TIS_SPI_CR50=y CONFIG_TCG_TIS_I2C_CR50=m CONFIG_TCG_TIS_I2C_INFINEON=y +CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y @@ -564,7 +612,6 @@ CONFIG_I2C_MUX_PINCTRL=m CONFIG_I2C_BCM2835=m CONFIG_I2C_CADENCE=m CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_GPIO=m CONFIG_I2C_IMX=y CONFIG_I2C_IMX_LPI2C=y @@ -631,8 +678,6 @@ CONFIG_SPMI=y CONFIG_SPMI_APPLE=m CONFIG_SPMI_MTK_PMIF=m CONFIG_PINCTRL_APPLE_GPIO=m -CONFIG_PINCTRL_BRCMSTB=y -CONFIG_PINCTRL_BCM2712=y CONFIG_PINCTRL_DA9062=m CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_RK805=m @@ -641,64 +686,11 @@ CONFIG_PINCTRL_SX150X=m CONFIG_PINCTRL_OWL=y CONFIG_PINCTRL_S700=y CONFIG_PINCTRL_S900=y -CONFIG_PINCTRL_IMX8MM=y -CONFIG_PINCTRL_IMX8MN=y -CONFIG_PINCTRL_IMX8MP=y -CONFIG_PINCTRL_IMX8MQ=y -CONFIG_PINCTRL_IMX8QM=y -CONFIG_PINCTRL_IMX8QXP=y -CONFIG_PINCTRL_IMX8DXL=y -CONFIG_PINCTRL_IMX8ULP=y -CONFIG_PINCTRL_IMX91=y -CONFIG_PINCTRL_IMX93=y +CONFIG_PINCTRL_BRCMSTB=y +CONFIG_PINCTRL_BCM2712=y +CONFIG_PINCTRL_SKY1=y CONFIG_PINCTRL_IMX_SCMI=y -CONFIG_PINCTRL_MSM=y -CONFIG_PINCTRL_ELIZA=y -CONFIG_PINCTRL_GLYMUR=y -CONFIG_PINCTRL_IPQ5018=y -CONFIG_PINCTRL_IPQ5210=y -CONFIG_PINCTRL_IPQ5332=y -CONFIG_PINCTRL_IPQ5424=y -CONFIG_PINCTRL_IPQ8074=y -CONFIG_PINCTRL_IPQ6018=y -CONFIG_PINCTRL_IPQ9574=y -CONFIG_PINCTRL_KAANAPALI=y -CONFIG_PINCTRL_MSM8916=y -CONFIG_PINCTRL_MSM8953=y -CONFIG_PINCTRL_MSM8976=y -CONFIG_PINCTRL_MSM8994=y -CONFIG_PINCTRL_MSM8996=y -CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_QCM2290=y -CONFIG_PINCTRL_QCS404=y -CONFIG_PINCTRL_QCS615=y -CONFIG_PINCTRL_QCS8300=y -CONFIG_PINCTRL_QDF2XXX=y -CONFIG_PINCTRL_QDU1000=y -CONFIG_PINCTRL_RP1=m -CONFIG_PINCTRL_SA8775P=y -CONFIG_PINCTRL_SC7180=y -CONFIG_PINCTRL_SC7280=y -CONFIG_PINCTRL_SC8180X=y -CONFIG_PINCTRL_SC8280XP=y -CONFIG_PINCTRL_SDM660=y -CONFIG_PINCTRL_SDM670=y -CONFIG_PINCTRL_SDM845=y -CONFIG_PINCTRL_SDX75=y -CONFIG_PINCTRL_SM4450=y -CONFIG_PINCTRL_SM6115=y -CONFIG_PINCTRL_SM6125=y -CONFIG_PINCTRL_SM6350=y -CONFIG_PINCTRL_SM6375=y -CONFIG_PINCTRL_MILOS=y -CONFIG_PINCTRL_SM8150=y -CONFIG_PINCTRL_SM8250=y -CONFIG_PINCTRL_SM8350=y -CONFIG_PINCTRL_SM8450=y -CONFIG_PINCTRL_SM8550=y -CONFIG_PINCTRL_SM8650=y -CONFIG_PINCTRL_SM8750=y -CONFIG_PINCTRL_X1E80100=y +CONFIG_PINCTRL_IMX91=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_LPASS_LPI=m CONFIG_PINCTRL_MILOS_LPASS_LPI=m @@ -711,6 +703,7 @@ CONFIG_PINCTRL_SM8550_LPASS_LPI=m CONFIG_PINCTRL_SM8650_LPASS_LPI=m CONFIG_PINCTRL_SOPHGO_SG2000=y CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_CADENCE=m CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_MB86S7X=y @@ -720,9 +713,9 @@ CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_SYSCON=y CONFIG_GPIO_UNIPHIER=y +CONFIG_GPIO_VF610=y CONFIG_GPIO_VISCONTI=y CONFIG_GPIO_WCD934X=m -CONFIG_GPIO_VF610=y CONFIG_GPIO_XGENE=y CONFIG_GPIO_XGENE_SB=y CONFIG_GPIO_XILINX=m @@ -730,9 +723,9 @@ CONFIG_GPIO_ZYNQ=m CONFIG_GPIO_MAX732X=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_ADP5585=m CONFIG_GPIO_PCF857X=m CONFIG_GPIO_TPIC2810=m +CONFIG_GPIO_ADP5585=m CONFIG_GPIO_BD9571MWV=m CONFIG_GPIO_MACSMC=m CONFIG_GPIO_MAX77620=y @@ -771,7 +764,6 @@ CONFIG_SENSORS_AMC6821=m CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA3221=m CONFIG_SENSORS_TMP102=m -CONFIG_MISC_RP1=m CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y CONFIG_DEVFREQ_THERMAL=y @@ -782,11 +774,6 @@ CONFIG_K3_THERMAL=m CONFIG_QORIQ_THERMAL=m CONFIG_SUN8I_THERMAL=y CONFIG_ROCKCHIP_THERMAL=m -CONFIG_RCAR_THERMAL=y -CONFIG_RCAR_GEN3_THERMAL=y -CONFIG_RZG2L_THERMAL=y -CONFIG_RZG3E_THERMAL=y -CONFIG_RZG3S_THERMAL=m CONFIG_ARMADA_THERMAL=y CONFIG_MTK_THERMAL=m CONFIG_MTK_LVTS_THERMAL=m @@ -794,6 +781,11 @@ CONFIG_BCM2711_THERMAL=m CONFIG_BCM2835_THERMAL=m CONFIG_BRCMSTB_THERMAL=m CONFIG_EXYNOS_THERMAL=y +CONFIG_RCAR_THERMAL=y +CONFIG_RCAR_GEN3_THERMAL=y +CONFIG_RZG2L_THERMAL=y +CONFIG_RZG3E_THERMAL=y +CONFIG_RZG3S_THERMAL=m CONFIG_TEGRA_SOCTHERM=m CONFIG_TEGRA_BPMP_THERMAL=m CONFIG_GENERIC_ADC_THERMAL=m @@ -919,10 +911,10 @@ CONFIG_SDR_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_AMPHION_VPU=m CONFIG_VIDEO_CADENCE_CSI2RX=m -CONFIG_VIDEO_MEDIATEK_JPEG=m -CONFIG_VIDEO_MEDIATEK_VCODEC=m CONFIG_VIDEO_WAVE_VPU=m CONFIG_VIDEO_E5010_JPEG_ENC=m +CONFIG_VIDEO_MEDIATEK_JPEG=m +CONFIG_VIDEO_MEDIATEK_VCODEC=m CONFIG_VIDEO_MEDIATEK_MDP3=m CONFIG_VIDEO_IMX7_CSI=m CONFIG_VIDEO_IMX_MIPI_CSIS=m @@ -932,8 +924,8 @@ CONFIG_VIDEO_IMX8_JPEG=m CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_QCOM_IRIS=m CONFIG_VIDEO_QCOM_VENUS=m -CONFIG_VIDEO_RCAR_ISP=m CONFIG_VIDEO_RCAR_CSI2=m +CONFIG_VIDEO_RCAR_ISP=m CONFIG_VIDEO_RCAR_VIN=m CONFIG_VIDEO_RZG2L_CSI2=m CONFIG_VIDEO_RZG2L_CRU=m @@ -941,8 +933,8 @@ CONFIG_VIDEO_RENESAS_FCP=m CONFIG_VIDEO_RENESAS_FDP1=m CONFIG_VIDEO_RENESAS_VSP1=m CONFIG_VIDEO_RCAR_DRIF=m -CONFIG_VIDEO_ROCKCHIP_CIF=m CONFIG_VIDEO_ROCKCHIP_RGA=m +CONFIG_VIDEO_ROCKCHIP_CIF=m CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m @@ -957,64 +949,12 @@ CONFIG_VIDEO_OV5640=m CONFIG_VIDEO_OV5645=m CONFIG_VIDEO_S5KJN1=m CONFIG_DRM=m -CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_HDLCD=m CONFIG_DRM_MALI_DISPLAY=m CONFIG_DRM_KOMEDA=m -CONFIG_DRM_NOUVEAU=m -CONFIG_DRM_EXYNOS=m -CONFIG_DRM_EXYNOS5433_DECON=y -CONFIG_DRM_EXYNOS7_DECON=y -CONFIG_DRM_EXYNOS_DSI=y -# CONFIG_DRM_EXYNOS_DP is not set -CONFIG_DRM_EXYNOS_HDMI=y -CONFIG_DRM_EXYNOS_MIC=y -CONFIG_DRM_ROCKCHIP=m -CONFIG_ROCKCHIP_VOP2=y -CONFIG_ROCKCHIP_ANALOGIX_DP=y -CONFIG_ROCKCHIP_CDN_DP=y -CONFIG_ROCKCHIP_DW_DP=y -CONFIG_ROCKCHIP_DW_HDMI=y -CONFIG_ROCKCHIP_DW_HDMI_QP=y -CONFIG_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_ROCKCHIP_INNO_HDMI=y -CONFIG_ROCKCHIP_LVDS=y -CONFIG_DRM_RCAR_DU=m -CONFIG_DRM_RCAR_DW_HDMI=m -CONFIG_DRM_RCAR_MIPI_DSI=m -CONFIG_DRM_RZG2L_MIPI_DSI=m -CONFIG_DRM_RZG2L_DU=m -CONFIG_DRM_SUN4I=m -CONFIG_DRM_SUN6I_DSI=m -CONFIG_DRM_SUN8I_DW_HDMI=m -CONFIG_DRM_SUN8I_MIXER=m -CONFIG_DRM_MSM=m -CONFIG_DRM_TEGRA=m -CONFIG_DRM_STM=m -CONFIG_DRM_STM_LVDS=m -CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m -CONFIG_DRM_PANEL_LVDS=m -CONFIG_DRM_PANEL_SIMPLE=m -CONFIG_DRM_PANEL_SUMMIT=m -CONFIG_DRM_PANEL_EDP=m -CONFIG_DRM_PANEL_HIMAX_HX8279=m -CONFIG_DRM_PANEL_HIMAX_HX83112A=m -CONFIG_DRM_PANEL_HIMAX_HX83112B=m -CONFIG_DRM_PANEL_ILITEK_ILI9882T=m -CONFIG_DRM_PANEL_KHADAS_TS050=m -CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m -CONFIG_DRM_PANEL_NOVATEK_NT36672A=m -CONFIG_DRM_PANEL_NOVATEK_NT36672E=m -CONFIG_DRM_PANEL_NOVATEK_NT37801=m -CONFIG_DRM_PANEL_RAYDIUM_RM67191=m -CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m -CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m -CONFIG_DRM_PANEL_SITRONIX_ST7703=m -CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m -CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m -CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_FSL_LDB=m +CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_ITE_IT6263=m CONFIG_DRM_LONTIUM_LT8912B=m CONFIG_DRM_LONTIUM_LT9611=m @@ -1023,7 +963,6 @@ CONFIG_DRM_LONTIUM_LT8713SX=m CONFIG_DRM_ITE_IT66121=m CONFIG_DRM_NWL_MIPI_DSI=m CONFIG_DRM_PARADE_PS8640=m -CONFIG_DRM_SAMSUNG_DSIM=m CONFIG_DRM_SII902X=m CONFIG_DRM_SIMPLE_BRIDGE=m CONFIG_DRM_THINE_THC63LVD1024=m @@ -1041,27 +980,74 @@ CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=m CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=m CONFIG_DRM_DW_HDMI_QP_CEC=y -CONFIG_DRM_IMX_DCSS=m -CONFIG_DRM_V3D=m -CONFIG_DRM_VC4=m CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_EXYNOS=m +CONFIG_DRM_EXYNOS5433_DECON=y +CONFIG_DRM_EXYNOS7_DECON=y +CONFIG_DRM_EXYNOS_DSI=y +# CONFIG_DRM_EXYNOS_DP is not set +CONFIG_DRM_EXYNOS_HDMI=y +CONFIG_DRM_EXYNOS_MIC=y CONFIG_DRM_HISI_HIBMC=m CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_POWERVR=m +CONFIG_DRM_IMX_DCSS=m +CONFIG_DRM_LIMA=m CONFIG_DRM_MEDIATEK=m CONFIG_DRM_MEDIATEK_DP=m CONFIG_DRM_MEDIATEK_HDMI=m CONFIG_DRM_MEDIATEK_HDMI_V2=m +CONFIG_DRM_MESON=m +CONFIG_DRM_MSM=m CONFIG_DRM_MXSFB=m CONFIG_DRM_IMX_LCDIF=m -CONFIG_DRM_MESON=m -CONFIG_DRM_PL111=m -CONFIG_DRM_LIMA=m +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_HIMAX_HX8279=m +CONFIG_DRM_PANEL_HIMAX_HX83112A=m +CONFIG_DRM_PANEL_HIMAX_HX83112B=m +CONFIG_DRM_PANEL_ILITEK_ILI9882T=m +CONFIG_DRM_PANEL_KHADAS_TS050=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_NOVATEK_NT36672A=m +CONFIG_DRM_PANEL_NOVATEK_NT36672E=m +CONFIG_DRM_PANEL_NOVATEK_NT37801=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=m +CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m +CONFIG_DRM_PANEL_EDP=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_SUMMIT=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m CONFIG_DRM_PANFROST=m CONFIG_DRM_PANTHOR=m +CONFIG_DRM_PL111=m +CONFIG_DRM_RCAR_DU=m +CONFIG_DRM_RCAR_DW_HDMI=m +CONFIG_DRM_RZG2L_DU=m +CONFIG_DRM_ROCKCHIP=m +CONFIG_ROCKCHIP_VOP2=y +CONFIG_ROCKCHIP_ANALOGIX_DP=y +CONFIG_ROCKCHIP_CDN_DP=y +CONFIG_ROCKCHIP_DW_DP=y +CONFIG_ROCKCHIP_DW_HDMI=y +CONFIG_ROCKCHIP_DW_HDMI_QP=y +CONFIG_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_ROCKCHIP_INNO_HDMI=y +CONFIG_ROCKCHIP_LVDS=y +CONFIG_DRM_STM=m +CONFIG_DRM_STM_LVDS=m +CONFIG_DRM_SUN4I=m +CONFIG_DRM_TEGRA=m CONFIG_DRM_TIDSS=m +CONFIG_DRM_V3D=m +CONFIG_DRM_VC4=m CONFIG_DRM_ZYNQMP_DPSUB=m CONFIG_DRM_ZYNQMP_DPSUB_AUDIO=y -CONFIG_DRM_POWERVR=m CONFIG_FB=y CONFIG_FB_EFI=y CONFIG_FB_MODE_HELPERS=y @@ -1114,21 +1100,15 @@ CONFIG_SND_SOC_SC8280XP=m CONFIG_SND_SOC_SC7180=m CONFIG_SND_SOC_SC7280=m CONFIG_SND_SOC_X1E80100=m -CONFIG_SND_SOC_ROCKCHIP=m +CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SOC_MSIOF=m +CONFIG_SND_SOC_RZ=m CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m CONFIG_SND_SOC_ROCKCHIP_SAI=m CONFIG_SND_SOC_ROCKCHIP_SPDIF=m CONFIG_SND_SOC_ROCKCHIP_RT5645=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m -CONFIG_SND_SOC_RCAR=m -CONFIG_SND_SOC_MSIOF=m -CONFIG_SND_SOC_RZ=m CONFIG_SND_SOC_SAMSUNG=m -CONFIG_SND_SOC_SOF_TOPLEVEL=y -CONFIG_SND_SOC_SOF_OF=m -CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y -CONFIG_SND_SOC_SOF_MT8186=m -CONFIG_SND_SOC_SOF_MT8195=m CONFIG_SND_SUN8I_CODEC=m CONFIG_SND_SUN8I_CODEC_ANALOG=m CONFIG_SND_SUN50I_CODEC_ANALOG=m @@ -1148,11 +1128,15 @@ CONFIG_SND_SOC_TEGRA210_AMX=m CONFIG_SND_SOC_TEGRA210_ADX=m CONFIG_SND_SOC_TEGRA210_MIXER=m CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m -CONFIG_SND_SOC_DAVINCI_MCASP=m CONFIG_SND_SOC_J721E_EVM=m CONFIG_SND_SOC_XILINX_I2S=m CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m CONFIG_SND_SOC_XILINX_SPDIF=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y +CONFIG_SND_SOC_SOF_MT8186=m +CONFIG_SND_SOC_SOF_MT8195=m CONFIG_SND_SOC_AK4613=m CONFIG_SND_SOC_AK4619=m CONFIG_SND_SOC_DA7213=m @@ -1164,7 +1148,6 @@ CONFIG_SND_SOC_GTM601=m CONFIG_SND_SOC_MAX98090=m CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -CONFIG_SND_SOC_PCM3168A_I2C=m CONFIG_SND_SOC_RK3308=m CONFIG_SND_SOC_RK817=m CONFIG_SND_SOC_RT5640=m @@ -1221,12 +1204,10 @@ CONFIG_USB_CDNS_SUPPORT=m CONFIG_USB_CDNS3=m CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y -CONFIG_USB_CDNS3_IMX=m CONFIG_USB_MTU3=y CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SUNXI=y CONFIG_USB_DWC3=y -CONFIG_OMAP_USB2=m CONFIG_USB_DWC2=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y @@ -1312,6 +1293,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_OWL=y CONFIG_SCSI_UFSHCD=y CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_CRYPTO=y CONFIG_SCSI_UFSHCD_PLATFORM=y CONFIG_SCSI_UFS_CDNS_PLATFORM=m CONFIG_SCSI_UFS_QCOM=m @@ -1321,8 +1303,6 @@ CONFIG_SCSI_UFS_RENESAS=m CONFIG_SCSI_UFS_TI_J721E=m CONFIG_SCSI_UFS_EXYNOS=y CONFIG_SCSI_UFS_ROCKCHIP=y -CONFIG_BLK_INLINE_ENCRYPTION=y -CONFIG_SCSI_UFS_CRYPTO=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS_FLASH=m @@ -1349,9 +1329,9 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=m CONFIG_RTC_DRV_HYM8563=m CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_NVIDIA_VRS10=m CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_ISL1208=m -CONFIG_RTC_DRV_PCF85063=m CONFIG_RTC_DRV_PCF85363=m CONFIG_RTC_DRV_PCF8563=m CONFIG_RTC_DRV_M41T80=m @@ -1359,10 +1339,10 @@ CONFIG_RTC_DRV_BQ32K=m CONFIG_RTC_DRV_RX8581=m CONFIG_RTC_DRV_RV3028=m CONFIG_RTC_DRV_RV8803=m -CONFIG_RTC_DRV_S32G=m CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF85063=m CONFIG_RTC_DRV_DA9063=m CONFIG_RTC_DRV_EFI=y CONFIG_RTC_DRV_ZYNQMP=m @@ -1381,8 +1361,8 @@ CONFIG_RTC_DRV_MT6397=m CONFIG_RTC_DRV_XGENE=y CONFIG_RTC_DRV_TI_K3=m CONFIG_RTC_DRV_RENESAS_RTCA3=m -CONFIG_RTC_DRV_NVIDIA_VRS10=m CONFIG_RTC_DRV_MACSMC=m +CONFIG_RTC_DRV_S32G=m CONFIG_DMADEVICES=y CONFIG_APPLE_ADMAC=m CONFIG_DMA_BCM2835=y @@ -1433,11 +1413,11 @@ CONFIG_CROS_EC_RPMSG=m CONFIG_CROS_EC_SPI=y CONFIG_CROS_KBD_LED_BACKLIGHT=m CONFIG_CROS_EC_CHARDEV=m -CONFIG_COMMON_CLK_APPLE_NCO=m CONFIG_EC_ACER_ASPIRE1=m CONFIG_EC_HUAWEI_GAOKUN=m CONFIG_EC_LENOVO_YOGA_C630=m CONFIG_EC_LENOVO_THINKPAD_T14S=m +CONFIG_COMMON_CLK_APPLE_NCO=m CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_SCPI=y @@ -1445,7 +1425,6 @@ CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_FSL_SAI=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_COMMON_CLK_PWM=y -CONFIG_COMMON_CLK_RP1=m CONFIG_COMMON_CLK_RS9_PCIE=y CONFIG_COMMON_CLK_VC3=y CONFIG_COMMON_CLK_VC5=y @@ -1498,7 +1477,6 @@ CONFIG_QCOM_CLK_APCC_MSM8996=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y -CONFIG_IPQ_APSS_5018=y CONFIG_IPQ_CMN_PLL=m CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5210=y @@ -1522,17 +1500,16 @@ CONFIG_QCM_DISPCC_2290=m CONFIG_QCS_DISPCC_615=m CONFIG_QCS_CAMCC_615=m CONFIG_QCS_GCC_404=y -CONFIG_QCS_GCC_615=y -CONFIG_QCS_GCC_8300=y -CONFIG_SC_CAMCC_7280=m CONFIG_SA_CAMCC_8775P=m +CONFIG_QCS_GCC_8300=y +CONFIG_QCS_GCC_615=y CONFIG_QCS_GPUCC_615=m CONFIG_QCS_VIDEOCC_615=m -CONFIG_QDU_GCC_1000=y +CONFIG_SC_CAMCC_7280=m CONFIG_SC_CAMCC_8280XP=m +CONFIG_SA_DISPCC_8775P=m CONFIG_SC_DISPCC_7280=m CONFIG_SC_DISPCC_8280XP=m -CONFIG_SA_DISPCC_8775P=m CONFIG_SA_GCC_8775P=y CONFIG_SA_GPUCC_8775P=m CONFIG_SC_GCC_7180=y @@ -1545,6 +1522,7 @@ CONFIG_SC_LPASSCC_8280XP=m CONFIG_SC_LPASS_CORECC_7280=m CONFIG_SC_VIDEOCC_7280=m CONFIG_SDM_CAMCC_845=m +CONFIG_QDU_GCC_1000=y CONFIG_SDM_GPUCC_845=y CONFIG_SDM_VIDEOCC_845=y CONFIG_SDM_DISPCC_845=y @@ -1609,22 +1587,22 @@ CONFIG_RENESAS_OSTM=y CONFIG_ARM_MHU=y CONFIG_EXYNOS_MBOX=m CONFIG_IMX_MBOX=y -CONFIG_OMAP2PLUS_MBOX=m CONFIG_PLATFORM_MHU=y +CONFIG_OMAP2PLUS_MBOX=m CONFIG_BCM2835_MBOX=y CONFIG_QCOM_APCS_IPC=y +CONFIG_TEGRA_HSP_MBOX=y CONFIG_MTK_ADSP_MBOX=m CONFIG_QCOM_CPUCP_MBOX=m -CONFIG_TEGRA_HSP_MBOX=y CONFIG_QCOM_IPCC=y CONFIG_CIX_MBOX=y -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_ARM_SMMU=y CONFIG_ARM_SMMU_V3=y -CONFIG_MTK_IOMMU=y CONFIG_QCOM_IOMMU=y +CONFIG_ROCKCHIP_IOMMU=y +CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_APPLE_DART=m +CONFIG_MTK_IOMMU=y CONFIG_REMOTEPROC=y CONFIG_IMX_REMOTEPROC=y CONFIG_MTK_SCP=m @@ -1728,9 +1706,9 @@ CONFIG_PWM_BCM2835=m CONFIG_PWM_BRCMSTB=m CONFIG_PWM_CROS_EC=m CONFIG_PWM_IMX27=m +CONFIG_PWM_MEDIATEK=m CONFIG_PWM_MESON=m CONFIG_PWM_MTK_DISP=m -CONFIG_PWM_MEDIATEK=m CONFIG_PWM_RENESAS_RCAR=m CONFIG_PWM_RENESAS_RZG2L_GPT=m CONFIG_PWM_RENESAS_RZ_MTU3=m @@ -1758,10 +1736,10 @@ CONFIG_RESET_QCOM_PDC=m CONFIG_RESET_RZG2L_USBPHY_CTRL=y CONFIG_RESET_RZV2H_USB2PHY=m CONFIG_RESET_TI_SCI=y -CONFIG_PHY_SNPS_EUSB2=m -CONFIG_PHY_XGENE=y CONFIG_PHY_CAN_TRANSCEIVER=m CONFIG_PHY_NXP_PTN3222=m +CONFIG_PHY_SNPS_EUSB2=m +CONFIG_PHY_XGENE=y CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_CADENCE_TORRENT=m CONFIG_PHY_CADENCE_DPHY=m @@ -1812,6 +1790,7 @@ CONFIG_PHY_UNIPHIER_USB3=y CONFIG_PHY_TEGRA_XUSB=y CONFIG_PHY_AM654_SERDES=m CONFIG_PHY_J721E_WIZ=m +CONFIG_OMAP_USB2=m CONFIG_PHY_XILINX_ZYNQMP=m CONFIG_ARM_CCI_PMU=m CONFIG_ARM_CCN=m @@ -1855,7 +1834,6 @@ CONFIG_ALTERA_FREEZE_BRIDGE=m CONFIG_XILINX_PR_DECOUPLER=m CONFIG_FPGA_REGION=m CONFIG_OF_FPGA_REGION=m -CONFIG_OF_OVERLAY=y CONFIG_FPGA_MGR_ZYNQMP_FPGA=m CONFIG_FPGA_MGR_VERSAL_FPGA=m CONFIG_TEE=y @@ -1904,9 +1882,9 @@ CONFIG_INTERCONNECT_QCOM_SM8650=y CONFIG_INTERCONNECT_QCOM_SM8750=y CONFIG_INTERCONNECT_QCOM_X1E80100=y CONFIG_COUNTER=m -CONFIG_TI_EQEP=m CONFIG_RZ_MTU3_CNT=m CONFIG_STM32_TIMER_CNT=m +CONFIG_TI_EQEP=m CONFIG_HTE=y CONFIG_HTE_TEGRA194=y CONFIG_HTE_TEGRA194_TEST=m @@ -1935,13 +1913,13 @@ CONFIG_NFS_V4=y CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_ROOT_NFS=y -CONFIG_9P_FS=y +CONFIG_9P_FS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_SECURITY=y CONFIG_CRYPTO_USER=y -CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_BENCHMARK=m +CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_SHA3=m CONFIG_CRYPTO_SM3=m diff --git a/drivers/base/platform-msi.c b/drivers/base/platform-msi.c index 70db08f3ac6fa..69eed058eb208 100644 --- a/drivers/base/platform-msi.c +++ b/drivers/base/platform-msi.c @@ -61,10 +61,6 @@ static const struct msi_domain_template platform_msi_template = { * parent. The parent domain sets up the new domain. The domain has * a fixed size of @nvec. The domain is managed by devres and will * be removed when the device is removed. - * - * Note: For migration purposes this falls back to the original platform_msi code - * up to the point where all platforms have been converted to the MSI - * parent model. */ int platform_device_msi_init_and_alloc_irqs(struct device *dev, unsigned int nvec, irq_write_msi_msg_t write_msi_msg) diff --git a/drivers/bus/fsl-mc/dprc-driver.c b/drivers/bus/fsl-mc/dprc-driver.c index db67442addad2..a85706826fa06 100644 --- a/drivers/bus/fsl-mc/dprc-driver.c +++ b/drivers/bus/fsl-mc/dprc-driver.c @@ -609,9 +609,8 @@ int dprc_setup(struct fsl_mc_device *mc_dev) { struct device *parent_dev = mc_dev->dev.parent; struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - struct irq_domain *mc_msi_domain; + struct irq_domain *mc_msi_domain = NULL; bool mc_io_created = false; - bool msi_domain_set = false; bool uapi_created = false; u16 major_ver, minor_ver; size_t region_size; @@ -652,14 +651,12 @@ int dprc_setup(struct fsl_mc_device *mc_dev) uapi_created = true; } - mc_msi_domain = fsl_mc_find_msi_domain(&mc_dev->dev); - if (!mc_msi_domain) { + mc_msi_domain = fsl_mc_get_msi_parent(&mc_dev->dev); + if (!mc_msi_domain) dev_warn(&mc_dev->dev, "WARNING: MC bus without interrupt support\n"); - } else { + else dev_set_msi_domain(&mc_dev->dev, mc_msi_domain); - msi_domain_set = true; - } error = dprc_open(mc_dev->mc_io, 0, mc_dev->obj_desc.id, &mc_dev->mc_handle); @@ -699,8 +696,7 @@ error_cleanup_open: (void)dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); error_cleanup_msi_domain: - if (msi_domain_set) - dev_set_msi_domain(&mc_dev->dev, NULL); + dev_set_msi_domain(&mc_dev->dev, NULL); if (mc_io_created) { fsl_destroy_mc_io(mc_dev->mc_io); diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c index 221146e4860be..64d75eed0d347 100644 --- a/drivers/bus/fsl-mc/fsl-mc-bus.c +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c @@ -66,6 +66,13 @@ struct fsl_mc_addr_translation_range { #define GCR1_P1_STOP BIT(31) #define GCR1_P2_STOP BIT(30) +#define FSL_MC_GSR 0x8 +#define FSL_MC_GSR_BOOT_DONE BIT(0) +#define FSL_MC_GSR_MCS_MASK GENMASK(7, 0) +#define FSL_MC_GSR_MCS_ERR_MASK GENMASK(7, 1) +#define FSL_MC_GSR_BC_MASK GENMASK(15, 8) +#define FSL_MC_GSR_BC_SHIFT 8 + #define FSL_MC_FAPR 0x28 #define MC_FAPR_PL BIT(18) #define MC_FAPR_BMT BIT(17) @@ -828,14 +835,12 @@ int fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc, } else { /* * A non-DPRC object has to be a child of a DPRC, use the - * parent's ICID and interrupt domain. + * parent's ICID. */ mc_dev->icid = parent_mc_dev->icid; mc_dev->dma_mask = FSL_MC_DEFAULT_DMA_MASK; mc_dev->dev.dma_mask = &mc_dev->dma_mask; mc_dev->dev.coherent_dma_mask = mc_dev->dma_mask; - dev_set_msi_domain(&mc_dev->dev, - dev_get_msi_domain(&parent_mc_dev->dev)); } /* @@ -992,6 +997,41 @@ static int get_mc_addr_translation_ranges(struct device *dev, return 0; } +static u32 fsl_mc_read_gsr(struct fsl_mc *mc) +{ + return readl(mc->fsl_mc_regs + FSL_MC_GSR); +} + +static int fsl_mc_firmware_check(struct platform_device *pdev) +{ + struct fsl_mc *mc = platform_get_drvdata(pdev); + u32 gsr, boot_done, boot_code, mcs; + + gsr = fsl_mc_read_gsr(mc); + boot_code = (gsr & FSL_MC_GSR_BC_MASK) >> FSL_MC_GSR_BC_SHIFT; + if (boot_code == 0xDD) { + dev_err(&pdev->dev, + "fsl-mc: DPL processing was not started, DPAA2 will not work!\n"); + return -EOPNOTSUPP; + } + + boot_done = gsr & FSL_MC_GSR_BOOT_DONE; + if (!boot_done) { + dev_dbg(&pdev->dev, + "fsl-mc: DPL processing in progress, defer probe\n"); + return -EPROBE_DEFER; + } + + mcs = gsr & FSL_MC_GSR_MCS_MASK; + if (mcs & FSL_MC_GSR_MCS_ERR_MASK) { + dev_err(&pdev->dev, + "fsl-mc: MC boot completed with error 0x%x\n", mcs); + return -EINVAL; + } + + return 0; +} + /* * fsl_mc_bus_probe - callback invoked when the root MC bus is being * added @@ -1056,6 +1096,10 @@ static int fsl_mc_bus_probe(struct platform_device *pdev) mc->fsl_mc_regs + FSL_MC_GCR1); } + error = fsl_mc_firmware_check(pdev); + if (error) + return error; + /* * Get physical address of MC portal for the root DPRC: */ diff --git a/drivers/bus/fsl-mc/fsl-mc-msi.c b/drivers/bus/fsl-mc/fsl-mc-msi.c index 82cd69f7884c6..be38b43803dea 100644 --- a/drivers/bus/fsl-mc/fsl-mc-msi.c +++ b/drivers/bus/fsl-mc/fsl-mc-msi.c @@ -15,53 +15,16 @@ #include "fsl-mc-private.h" -#ifdef GENERIC_MSI_DOMAIN_OPS -/* - * Generate a unique ID identifying the interrupt (only used within the MSI - * irqdomain. Combine the icid with the interrupt index. - */ -static irq_hw_number_t fsl_mc_domain_calc_hwirq(struct fsl_mc_device *dev, - struct msi_desc *desc) -{ - /* - * Make the base hwirq value for ICID*10000 so it is readable - * as a decimal value in /proc/interrupts. - */ - return (irq_hw_number_t)(desc->msi_index + (dev->icid * 10000)); -} - -static void fsl_mc_msi_set_desc(msi_alloc_info_t *arg, - struct msi_desc *desc) -{ - arg->desc = desc; - arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev), - desc); -} -#else -#define fsl_mc_msi_set_desc NULL -#endif - -static void fsl_mc_msi_update_dom_ops(struct msi_domain_info *info) +static void fsl_mc_write_msi_msg(struct msi_desc *msi_desc, struct msi_msg *msg) { - struct msi_domain_ops *ops = info->ops; - - if (!ops) - return; - - /* - * set_desc should not be set by the caller - */ - if (!ops->set_desc) - ops->set_desc = fsl_mc_msi_set_desc; -} - -static void __fsl_mc_msi_write_msg(struct fsl_mc_device *mc_bus_dev, - struct fsl_mc_device_irq *mc_dev_irq, - struct msi_desc *msi_desc) -{ - int error; + struct fsl_mc_device *mc_bus_dev = to_fsl_mc_device(msi_desc->dev); + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); + struct fsl_mc_device_irq *mc_dev_irq = &mc_bus->irq_resources[msi_desc->msi_index]; struct fsl_mc_device *owner_mc_dev = mc_dev_irq->mc_dev; struct dprc_irq_cfg irq_cfg; + int error; + + msi_desc->msg = *msg; /* * msi_desc->msg.address is 0x0 when this function is invoked in @@ -110,118 +73,27 @@ static void __fsl_mc_msi_write_msg(struct fsl_mc_device *mc_bus_dev, } } -/* - * NOTE: This function is invoked with interrupts disabled - */ -static void fsl_mc_msi_write_msg(struct irq_data *irq_data, - struct msi_msg *msg) -{ - struct msi_desc *msi_desc = irq_data_get_msi_desc(irq_data); - struct fsl_mc_device *mc_bus_dev = to_fsl_mc_device(msi_desc->dev); - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); - struct fsl_mc_device_irq *mc_dev_irq = - &mc_bus->irq_resources[msi_desc->msi_index]; - - msi_desc->msg = *msg; - - /* - * Program the MSI (paddr, value) pair in the device: - */ - __fsl_mc_msi_write_msg(mc_bus_dev, mc_dev_irq, msi_desc); -} - -static void fsl_mc_msi_update_chip_ops(struct msi_domain_info *info) -{ - struct irq_chip *chip = info->chip; - - if (!chip) - return; - - /* - * irq_write_msi_msg should not be set by the caller - */ - if (!chip->irq_write_msi_msg) - chip->irq_write_msi_msg = fsl_mc_msi_write_msg; -} - -/** - * fsl_mc_msi_create_irq_domain - Create a fsl-mc MSI interrupt domain - * @fwnode: Optional firmware node of the interrupt controller - * @info: MSI domain info - * @parent: Parent irq domain - * - * Updates the domain and chip ops and creates a fsl-mc MSI - * interrupt domain. - * - * Returns: - * A domain pointer or NULL in case of failure. - */ -struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, - struct msi_domain_info *info, - struct irq_domain *parent) -{ - struct irq_domain *domain; - - if (WARN_ON((info->flags & MSI_FLAG_LEVEL_CAPABLE))) - info->flags &= ~MSI_FLAG_LEVEL_CAPABLE; - if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) - fsl_mc_msi_update_dom_ops(info); - if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) - fsl_mc_msi_update_chip_ops(info); - info->flags |= MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS | MSI_FLAG_FREE_MSI_DESCS; - - domain = msi_create_irq_domain(fwnode, info, parent); - if (domain) - irq_domain_update_bus_token(domain, DOMAIN_BUS_FSL_MC_MSI); - - return domain; -} - -struct irq_domain *fsl_mc_find_msi_domain(struct device *dev) +struct irq_domain *fsl_mc_get_msi_parent(struct device *dev) { + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); struct device *root_dprc_dev; struct device *bus_dev; - struct irq_domain *msi_domain; - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); fsl_mc_get_root_dprc(dev, &root_dprc_dev); bus_dev = root_dprc_dev->parent; - if (bus_dev->of_node) { - msi_domain = of_msi_map_get_device_domain(dev, - mc_dev->icid, - DOMAIN_BUS_FSL_MC_MSI); - - /* - * if the msi-map property is missing assume that all the - * child containers inherit the domain from the parent - */ - if (!msi_domain) - - msi_domain = of_msi_get_domain(bus_dev, - bus_dev->of_node, - DOMAIN_BUS_FSL_MC_MSI); - } else { - msi_domain = iort_get_device_domain(dev, mc_dev->icid, - DOMAIN_BUS_FSL_MC_MSI); - } - - return msi_domain; + return (bus_dev->of_node ? + of_msi_get_domain(bus_dev, bus_dev->of_node, DOMAIN_BUS_NEXUS) : + iort_get_device_domain(bus_dev, mc_dev->icid, DOMAIN_BUS_NEXUS)); } int fsl_mc_msi_domain_alloc_irqs(struct device *dev, unsigned int irq_count) { int error = msi_setup_device_data(dev); - if (error) return error; - /* - * NOTE: Calling this function will trigger the invocation of the - * its_fsl_mc_msi_prepare() callback - */ - error = msi_domain_alloc_irqs_range(dev, MSI_DEFAULT_DOMAIN, 0, irq_count - 1); - + error = platform_device_msi_init_and_alloc_irqs(dev, irq_count, fsl_mc_write_msi_msg); if (error) dev_err(dev, "Failed to allocate IRQs\n"); return error; @@ -231,3 +103,15 @@ void fsl_mc_msi_domain_free_irqs(struct device *dev) { msi_domain_free_irqs_all(dev, MSI_DEFAULT_DOMAIN); } + +u32 fsl_mc_get_msi_id(struct device *dev) +{ + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + struct device *root_dprc_dev; + + fsl_mc_get_root_dprc(dev, &root_dprc_dev); + + return (root_dprc_dev->parent->of_node ? + of_msi_xlate(dev, NULL, mc_dev->icid) : + iort_msi_map_id(dev, mc_dev->icid)); +} diff --git a/drivers/bus/fsl-mc/fsl-mc-private.h b/drivers/bus/fsl-mc/fsl-mc-private.h index beed4c53533d8..197edcc8cde46 100644 --- a/drivers/bus/fsl-mc/fsl-mc-private.h +++ b/drivers/bus/fsl-mc/fsl-mc-private.h @@ -641,7 +641,7 @@ int fsl_mc_msi_domain_alloc_irqs(struct device *dev, void fsl_mc_msi_domain_free_irqs(struct device *dev); -struct irq_domain *fsl_mc_find_msi_domain(struct device *dev); +struct irq_domain *fsl_mc_get_msi_parent(struct device *dev); int __must_check fsl_create_mc_io(struct device *dev, phys_addr_t mc_portal_phys_addr, diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index e755a2a052096..753e8fc3b916c 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -51,12 +51,6 @@ config ARM_GIC_V3_ITS default ARM_GIC_V3 select IRQ_MSI_IOMMU -config ARM_GIC_V3_ITS_FSL_MC - bool - depends on ARM_GIC_V3_ITS - depends on FSL_MC_BUS - default ARM_GIC_V3_ITS - config ARM_GIC_V5 bool select IRQ_DOMAIN_HIERARCHY diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 26aa3b6ec99fd..d5a28cee0d8eb 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -35,7 +35,6 @@ obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_ITS_PARENT) += irq-gic-its-msi-parent.o obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v4.o -obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o obj-$(CONFIG_ARM_GIC_V5) += irq-gic-v5.o irq-gic-v5-irs.o irq-gic-v5-its.o \ irq-gic-v5-iwb.o obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq-gic-its-msi-parent.c index a832cdb2e6978..d36b278ae66c5 100644 --- a/drivers/irqchip/irq-gic-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-its-msi-parent.c @@ -5,6 +5,7 @@ // Copyright (C) 2022 Intel #include <linux/acpi_iort.h> +#include <linux/fsl/mc.h> #include <linux/of_address.h> #include <linux/pci.h> @@ -187,9 +188,11 @@ static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev, { struct msi_domain_info *msi_info; u32 dev_id; - int ret; + int ret = 0; - if (dev->of_node) + if (dev_is_fsl_mc(dev)) + dev_id = fsl_mc_get_msi_id(dev); + else if (dev->of_node) ret = of_pmsi_get_msi_info(domain->parent, dev, &dev_id, NULL); else ret = iort_pmsi_get_msi_info(dev, &dev_id, NULL); diff --git a/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c b/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c deleted file mode 100644 index b5785472765a3..0000000000000 --- a/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c +++ /dev/null @@ -1,168 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Freescale Management Complex (MC) bus driver MSI support - * - * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. - * Author: German Rivera <German.Rivera@freescale.com> - * - */ - -#include <linux/acpi.h> -#include <linux/acpi_iort.h> -#include <linux/irq.h> -#include <linux/msi.h> -#include <linux/of.h> -#include <linux/of_irq.h> -#include <linux/fsl/mc.h> - -static struct irq_chip its_msi_irq_chip = { - .name = "ITS-fMSI", - .irq_mask = irq_chip_mask_parent, - .irq_unmask = irq_chip_unmask_parent, - .irq_eoi = irq_chip_eoi_parent, - .irq_set_affinity = msi_domain_set_affinity -}; - -static u32 fsl_mc_msi_domain_get_msi_id(struct irq_domain *domain, - struct fsl_mc_device *mc_dev) -{ - struct device_node *of_node; - u32 out_id; - - of_node = irq_domain_get_of_node(domain); - out_id = of_node ? of_msi_xlate(&mc_dev->dev, &of_node, mc_dev->icid) : - iort_msi_map_id(&mc_dev->dev, mc_dev->icid); - - return out_id; -} - -static int its_fsl_mc_msi_prepare(struct irq_domain *msi_domain, - struct device *dev, - int nvec, msi_alloc_info_t *info) -{ - struct fsl_mc_device *mc_bus_dev; - struct msi_domain_info *msi_info; - - if (!dev_is_fsl_mc(dev)) - return -EINVAL; - - mc_bus_dev = to_fsl_mc_device(dev); - if (!(mc_bus_dev->flags & FSL_MC_IS_DPRC)) - return -EINVAL; - - /* - * Set the device Id to be passed to the GIC-ITS: - * - * NOTE: This device id corresponds to the IOMMU stream ID - * associated with the DPRC object (ICID). - */ - info->scratchpad[0].ul = fsl_mc_msi_domain_get_msi_id(msi_domain, - mc_bus_dev); - msi_info = msi_get_domain_info(msi_domain->parent); - - /* Allocate at least 32 MSIs, and always as a power of 2 */ - nvec = max_t(int, 32, roundup_pow_of_two(nvec)); - return msi_info->ops->msi_prepare(msi_domain->parent, dev, nvec, info); -} - -static struct msi_domain_ops its_fsl_mc_msi_ops __ro_after_init = { - .msi_prepare = its_fsl_mc_msi_prepare, -}; - -static struct msi_domain_info its_fsl_mc_msi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), - .ops = &its_fsl_mc_msi_ops, - .chip = &its_msi_irq_chip, -}; - -static const struct of_device_id its_device_id[] = { - { .compatible = "arm,gic-v3-its", }, - {}, -}; - -static void __init its_fsl_mc_msi_init_one(struct fwnode_handle *handle, - const char *name) -{ - struct irq_domain *parent; - struct irq_domain *mc_msi_domain; - - parent = irq_find_matching_fwnode(handle, DOMAIN_BUS_NEXUS); - if (!parent || !msi_get_domain_info(parent)) { - pr_err("%s: unable to locate ITS domain\n", name); - return; - } - - mc_msi_domain = fsl_mc_msi_create_irq_domain(handle, - &its_fsl_mc_msi_domain_info, - parent); - if (!mc_msi_domain) { - pr_err("%s: unable to create fsl-mc domain\n", name); - return; - } - - pr_info("fsl-mc MSI: %s domain created\n", name); -} - -#ifdef CONFIG_ACPI -static int __init -its_fsl_mc_msi_parse_madt(union acpi_subtable_headers *header, - const unsigned long end) -{ - struct acpi_madt_generic_translator *its_entry; - struct fwnode_handle *dom_handle; - const char *node_name; - int err = 0; - - its_entry = (struct acpi_madt_generic_translator *)header; - node_name = kasprintf(GFP_KERNEL, "ITS@0x%lx", - (long)its_entry->base_address); - - dom_handle = iort_find_domain_token(its_entry->translation_id); - if (!dom_handle) { - pr_err("%s: Unable to locate ITS domain handle\n", node_name); - err = -ENXIO; - goto out; - } - - its_fsl_mc_msi_init_one(dom_handle, node_name); - -out: - kfree(node_name); - return err; -} - - -static void __init its_fsl_mc_acpi_msi_init(void) -{ - acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, - its_fsl_mc_msi_parse_madt, 0); -} -#else -static inline void its_fsl_mc_acpi_msi_init(void) { } -#endif - -static void __init its_fsl_mc_of_msi_init(void) -{ - struct device_node *np; - - for (np = of_find_matching_node(NULL, its_device_id); np; - np = of_find_matching_node(np, its_device_id)) { - if (!of_device_is_available(np)) - continue; - if (!of_property_read_bool(np, "msi-controller")) - continue; - - its_fsl_mc_msi_init_one(of_fwnode_handle(np), - np->full_name); - } -} - -static int __init its_fsl_mc_msi_init(void) -{ - its_fsl_mc_of_msi_init(); - its_fsl_mc_acpi_msi_init(); - - return 0; -} - -early_initcall(its_fsl_mc_msi_init); diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index 70b6eddb867b9..3ecc4ce9cfa25 100644 --- a/drivers/soc/fsl/qe/qe.c +++ b/drivers/soc/fsl/qe/qe.c @@ -89,6 +89,9 @@ void qe_reset(void) if (qe_immr == NULL) qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE); + if (!qe_immr) + panic("QE:ioremap failed!"); + qe_snums_init(); qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID, diff --git a/drivers/soc/fsl/qe/qe_ports_ic.c b/drivers/soc/fsl/qe/qe_ports_ic.c index 8e2107e2cde5b..9b0bba64e91e4 100644 --- a/drivers/soc/fsl/qe/qe_ports_ic.c +++ b/drivers/soc/fsl/qe/qe_ports_ic.c @@ -17,6 +17,7 @@ struct qepic_data { void __iomem *reg; struct irq_domain *host; + int irq; }; static void qepic_mask(struct irq_data *d) @@ -92,11 +93,18 @@ static const struct irq_domain_ops qepic_host_ops = { .map = qepic_host_map, }; +static void qepic_remove(void *res) +{ + struct qepic_data *data = res; + + irq_set_chained_handler_and_data(data->irq, NULL, NULL); + irq_domain_remove(data->host); +} + static int qepic_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct qepic_data *data; - int irq; data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) @@ -106,17 +114,18 @@ static int qepic_probe(struct platform_device *pdev) if (IS_ERR(data->reg)) return PTR_ERR(data->reg); - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; + data->irq = platform_get_irq(pdev, 0); + if (data->irq < 0) + return data->irq; - data->host = irq_domain_add_linear(dev->of_node, 32, &qepic_host_ops, data); + data->host = irq_domain_create_linear(dev_fwnode(dev), 32, &qepic_host_ops, data); if (!data->host) return -ENODEV; - irq_set_chained_handler_and_data(irq, qepic_cascade, data); + irq_set_chained_handler_and_data(data->irq, qepic_cascade, data); + + return devm_add_action_or_reset(dev, qepic_remove, data); - return 0; } static const struct of_device_id qepic_match[] = { diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 26bed0fdceb00..2ab150d04bb1f 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -465,6 +465,15 @@ config ARCH_R9A07G043 endif # RISCV +config RCAR_MFIS + tristate "Renesas R-Car MFIS driver" + depends on ARCH_RENESAS || COMPILE_TEST + depends on MAILBOX + help + Select this option to enable the Renesas R-Car MFIS core driver for + the MFIS device found on SoCs like R-Car. On families like Gen5, this + is needed to communicate with the SCP. + config PWC_RZV2M bool "Renesas RZ/V2M PWC support" if COMPILE_TEST diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 655dbcb087472..81bde85c2178a 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_SYS_R9A09G057) += r9a09g057-sys.o # Family obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o +obj-$(CONFIG_RCAR_MFIS) += rcar-mfis.o obj-$(CONFIG_RST_RCAR) += rcar-rst.o obj-$(CONFIG_RZN1_IRQMUX) += rzn1_irqmux.o obj-$(CONFIG_SYSC_RZ) += rz-sysc.o diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a08g045-sysc.c index 03d653d5cde55..63e4aa6a7cd01 100644 --- a/drivers/soc/renesas/r9a08g045-sysc.c +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -37,18 +37,14 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initc .specific_id_mask = GENMASK(27, 0), }; -static bool rzg3s_regmap_readable_reg(struct device *dev, unsigned int reg) +static bool rzg3s_regmap_readable_writeable_reg(unsigned int reg) { switch (reg) { case SYS_XSPI_MAP_STAADD_CS0: case SYS_XSPI_MAP_ENDADD_CS0: case SYS_XSPI_MAP_STAADD_CS1: case SYS_XSPI_MAP_ENDADD_CS1: - case SYS_GETH0_CFG: - case SYS_GETH1_CFG: case SYS_PCIE_CFG: - case SYS_PCIE_MON: - case SYS_PCIE_ERR_MON: case SYS_PCIE_PHY: case SYS_I2C0_CFG: case SYS_I2C1_CFG: @@ -63,28 +59,27 @@ static bool rzg3s_regmap_readable_reg(struct device *dev, unsigned int reg) } } -static bool rzg3s_regmap_writeable_reg(struct device *dev, unsigned int reg) +static bool rzg3s_regmap_readable_reg(struct device *dev, unsigned int reg) { + if (rzg3s_regmap_readable_writeable_reg(reg)) + return true; + switch (reg) { - case SYS_XSPI_MAP_STAADD_CS0: - case SYS_XSPI_MAP_ENDADD_CS0: - case SYS_XSPI_MAP_STAADD_CS1: - case SYS_XSPI_MAP_ENDADD_CS1: - case SYS_PCIE_CFG: - case SYS_PCIE_PHY: - case SYS_I2C0_CFG: - case SYS_I2C1_CFG: - case SYS_I2C2_CFG: - case SYS_I2C3_CFG: - case SYS_I3C_CFG: - case SYS_USB_PWRRDY: - case SYS_PCIE_RST_RSM_B: + case SYS_GETH0_CFG: + case SYS_GETH1_CFG: + case SYS_PCIE_MON: + case SYS_PCIE_ERR_MON: return true; default: return false; } } +static bool rzg3s_regmap_writeable_reg(struct device *dev, unsigned int reg) +{ + return rzg3s_regmap_readable_writeable_reg(reg); +} + const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = { .soc_id_init_data = &rzg3s_sysc_soc_id_init_data, .readable_reg = rzg3s_regmap_readable_reg, diff --git a/drivers/soc/renesas/r9a08g046-sysc.c b/drivers/soc/renesas/r9a08g046-sysc.c index fd98df196d0a5..90db9d3835395 100644 --- a/drivers/soc/renesas/r9a08g046-sysc.c +++ b/drivers/soc/renesas/r9a08g046-sysc.c @@ -28,17 +28,14 @@ #define SYS_PWRRDY_N 0xd70 #define SYS_IPCONT_SEL_CLONECH 0xe2c -static bool rzg3l_regmap_readable_reg(struct device *dev, unsigned int reg) +static bool rzg3l_regmap_readable_writeable_reg(unsigned int reg) { switch (reg) { case SYS_XSPI_MAP_STAADD_CS0: case SYS_XSPI_MAP_ENDADD_CS0: case SYS_XSPI_MAP_STAADD_CS1: case SYS_XSPI_MAP_ENDADD_CS1: - case SYS_GETH0_CFG: - case SYS_GETH1_CFG: case SYS_PCIE_CFG: - case SYS_PCIE_MON: case SYS_PCIE_PHY: case SYS_I2C0_CFG: case SYS_I2C1_CFG: @@ -53,28 +50,26 @@ static bool rzg3l_regmap_readable_reg(struct device *dev, unsigned int reg) } } -static bool rzg3l_regmap_writeable_reg(struct device *dev, unsigned int reg) +static bool rzg3l_regmap_readable_reg(struct device *dev, unsigned int reg) { + if (rzg3l_regmap_readable_writeable_reg(reg)) + return true; + switch (reg) { - case SYS_XSPI_MAP_STAADD_CS0: - case SYS_XSPI_MAP_ENDADD_CS0: - case SYS_XSPI_MAP_STAADD_CS1: - case SYS_XSPI_MAP_ENDADD_CS1: - case SYS_PCIE_CFG: - case SYS_PCIE_PHY: - case SYS_I2C0_CFG: - case SYS_I2C1_CFG: - case SYS_I2C2_CFG: - case SYS_I2C3_CFG: - case SYS_I3C_CFG: - case SYS_PWRRDY_N: - case SYS_IPCONT_SEL_CLONECH: + case SYS_GETH0_CFG: + case SYS_GETH1_CFG: + case SYS_PCIE_MON: return true; default: return false; } } +static bool rzg3l_regmap_writeable_reg(struct device *dev, unsigned int reg) +{ + return rzg3l_regmap_readable_writeable_reg(reg); +} + static const struct rz_sysc_soc_id_init_data rzg3l_sysc_soc_id_init_data __initconst = { .family = "RZ/G3L", .id = 0x87d9447, diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a09g047-sys.c index ea3ca10fcc33f..b617fb0bde7b8 100644 --- a/drivers/soc/renesas/r9a09g047-sys.c +++ b/drivers/soc/renesas/r9a09g047-sys.c @@ -83,11 +83,9 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initco .print_id = rzg3e_sys_print_id, }; -static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg) +static bool rzg3e_regmap_readable_writeable_reg(unsigned int reg) { switch (reg) { - case SYS_LSI_OTPTSU1TRMVAL0: - case SYS_LSI_OTPTSU1TRMVAL1: case SYS_SPI_STAADDCS0: case SYS_SPI_ENDADDCS0: case SYS_SPI_STAADDCS1: @@ -112,33 +110,25 @@ static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg) } } -static bool rzg3e_regmap_writeable_reg(struct device *dev, unsigned int reg) +static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg) { + if (rzg3e_regmap_readable_writeable_reg(reg)) + return true; + switch (reg) { - case SYS_SPI_STAADDCS0: - case SYS_SPI_ENDADDCS0: - case SYS_SPI_STAADDCS1: - case SYS_SPI_ENDADDCS1: - case SYS_VSP_CLK: - case SYS_GBETH0_CFG: - case SYS_GBETH1_CFG: - case SYS_PCIE_INTX_CH0: - case SYS_PCIE_MSI1_CH0: - case SYS_PCIE_MSI2_CH0: - case SYS_PCIE_MSI3_CH0: - case SYS_PCIE_MSI4_CH0: - case SYS_PCIE_MSI5_CH0: - case SYS_PCIE_PME_CH0: - case SYS_PCIE_ACK_CH0: - case SYS_PCIE_MISC_CH0: - case SYS_PCIE_MODE_CH0: - case SYS_ADC_CFG: + case SYS_LSI_OTPTSU1TRMVAL0: + case SYS_LSI_OTPTSU1TRMVAL1: return true; default: return false; } } +static bool rzg3e_regmap_writeable_reg(struct device *dev, unsigned int reg) +{ + return rzg3e_regmap_readable_writeable_reg(reg); +} + const struct rz_sysc_init_data rzg3e_sys_init_data __initconst = { .soc_id_init_data = &rzg3e_sys_soc_id_init_data, .readable_reg = rzg3e_regmap_readable_reg, diff --git a/drivers/soc/renesas/r9a09g056-sys.c b/drivers/soc/renesas/r9a09g056-sys.c index 2a8ebc2099610..e6a66688423ff 100644 --- a/drivers/soc/renesas/r9a09g056-sys.c +++ b/drivers/soc/renesas/r9a09g056-sys.c @@ -88,13 +88,9 @@ static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initco .print_id = rzv2n_sys_print_id, }; -static bool rzv2n_regmap_readable_reg(struct device *dev, unsigned int reg) +static bool rzv2n_regmap_readable_writeable_reg(unsigned int reg) { switch (reg) { - case SYS_LSI_OTPTSU0TRMVAL0: - case SYS_LSI_OTPTSU0TRMVAL1: - case SYS_LSI_OTPTSU1TRMVAL0: - case SYS_LSI_OTPTSU1TRMVAL1: case SYS_GBETH0_CFG: case SYS_GBETH1_CFG: case SYS_PCIE_INTX_CH0: @@ -114,28 +110,27 @@ static bool rzv2n_regmap_readable_reg(struct device *dev, unsigned int reg) } } -static bool rzv2n_regmap_writeable_reg(struct device *dev, unsigned int reg) +static bool rzv2n_regmap_readable_reg(struct device *dev, unsigned int reg) { + if (rzv2n_regmap_readable_writeable_reg(reg)) + return true; + switch (reg) { - case SYS_GBETH0_CFG: - case SYS_GBETH1_CFG: - case SYS_PCIE_INTX_CH0: - case SYS_PCIE_MSI1_CH0: - case SYS_PCIE_MSI2_CH0: - case SYS_PCIE_MSI3_CH0: - case SYS_PCIE_MSI4_CH0: - case SYS_PCIE_MSI5_CH0: - case SYS_PCIE_PME_CH0: - case SYS_PCIE_ACK_CH0: - case SYS_PCIE_MISC_CH0: - case SYS_PCIE_MODE_CH0: - case SYS_ADC_CFG: + case SYS_LSI_OTPTSU0TRMVAL0: + case SYS_LSI_OTPTSU0TRMVAL1: + case SYS_LSI_OTPTSU1TRMVAL0: + case SYS_LSI_OTPTSU1TRMVAL1: return true; default: return false; } } +static bool rzv2n_regmap_writeable_reg(struct device *dev, unsigned int reg) +{ + return rzv2n_regmap_readable_writeable_reg(reg); +} + const struct rz_sysc_init_data rzv2n_sys_init_data __initconst = { .soc_id_init_data = &rzv2n_sys_soc_id_init_data, .readable_reg = rzv2n_regmap_readable_reg, diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a09g057-sys.c index f3e054206acbd..308492c31acbb 100644 --- a/drivers/soc/renesas/r9a09g057-sys.c +++ b/drivers/soc/renesas/r9a09g057-sys.c @@ -91,13 +91,9 @@ static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __initco .print_id = rzv2h_sys_print_id, }; -static bool rzv2h_regmap_readable_reg(struct device *dev, unsigned int reg) +static bool rzv2h_regmap_readable_writeable_reg(unsigned int reg) { switch (reg) { - case SYS_LSI_OTPTSU0TRMVAL0: - case SYS_LSI_OTPTSU0TRMVAL1: - case SYS_LSI_OTPTSU1TRMVAL0: - case SYS_LSI_OTPTSU1TRMVAL1: case SYS_GBETH0_CFG: case SYS_GBETH1_CFG: case SYS_PCIE_INTX_CH0: @@ -128,39 +124,27 @@ static bool rzv2h_regmap_readable_reg(struct device *dev, unsigned int reg) } } -static bool rzv2h_regmap_writeable_reg(struct device *dev, unsigned int reg) +static bool rzv2h_regmap_readable_reg(struct device *dev, unsigned int reg) { + if (rzv2h_regmap_readable_writeable_reg(reg)) + return true; + switch (reg) { - case SYS_GBETH0_CFG: - case SYS_GBETH1_CFG: - case SYS_PCIE_INTX_CH0: - case SYS_PCIE_MSI1_CH0: - case SYS_PCIE_MSI2_CH0: - case SYS_PCIE_MSI3_CH0: - case SYS_PCIE_MSI4_CH0: - case SYS_PCIE_MSI5_CH0: - case SYS_PCIE_PME_CH0: - case SYS_PCIE_ACK_CH0: - case SYS_PCIE_MISC_CH0: - case SYS_PCIE_MODE_CH0: - case SYS_PCIE_INTX_CH1: - case SYS_PCIE_MSI1_CH1: - case SYS_PCIE_MSI2_CH1: - case SYS_PCIE_MSI3_CH1: - case SYS_PCIE_MSI4_CH1: - case SYS_PCIE_MSI5_CH1: - case SYS_PCIE_PME_CH1: - case SYS_PCIE_ACK_CH1: - case SYS_PCIE_MISC_CH1: - case SYS_PCIE_MODE_CH1: - case SYS_PCIE_MODE: - case SYS_ADC_CFG: + case SYS_LSI_OTPTSU0TRMVAL0: + case SYS_LSI_OTPTSU0TRMVAL1: + case SYS_LSI_OTPTSU1TRMVAL0: + case SYS_LSI_OTPTSU1TRMVAL1: return true; default: return false; } } +static bool rzv2h_regmap_writeable_reg(struct device *dev, unsigned int reg) +{ + return rzv2h_regmap_readable_writeable_reg(reg); +} + const struct rz_sysc_init_data rzv2h_sys_init_data __initconst = { .soc_id_init_data = &rzv2h_sys_soc_id_init_data, .readable_reg = rzv2h_regmap_readable_reg, diff --git a/drivers/soc/renesas/rcar-mfis.c b/drivers/soc/renesas/rcar-mfis.c new file mode 100644 index 0000000000000..b334b35306ae1 --- /dev/null +++ b/drivers/soc/renesas/rcar-mfis.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Renesas R-Car MFIS (Multifunctional Interface) driver + * + * Copyright (C) Renesas Solutions Corp. + * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * Wolfram Sang <wsa+renesas@sang-engineering.com> + */ +#include <dt-bindings/soc/renesas,r8a78000-mfis.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mailbox_controller.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#define MFISWPCNTR 0x0900 +#define MFISWACNTR 0x0904 + +#define MFIS_X5H_IICR(i) ((i) * 0x1000 + 0x00) +#define MFIS_X5H_EICR(i) ((i) * 0x1000 + 0x04) + +#define MFIS_UNPROTECT_KEY 0xACCE0000 + +struct mfis_priv; + +struct mfis_reg { + void __iomem *base; + resource_size_t start; + struct mfis_priv *priv; +}; + +struct mfis_info { + u32 unprotect_mask; + unsigned int mb_num_channels; + unsigned int mb_reg_comes_from_dt:1; + unsigned int mb_tx_uses_eicr:1; + unsigned int mb_channels_are_unidir:1; +}; + +struct mfis_chan_priv { + u32 reg; + int irq; +}; + +struct mfis_priv { + spinlock_t unprotect_lock; /* guards access to the unprotection reg */ + struct device *dev; + struct mfis_reg common_reg; + struct mfis_reg mbox_reg; + const struct mfis_info *info; + + /* mailbox private data */ + struct mbox_controller mbox; + struct mfis_chan_priv *chan_privs; +}; + +static u32 mfis_read(struct mfis_reg *mreg, unsigned int reg) +{ + return ioread32(mreg->base + reg); +} + +static void mfis_write(struct mfis_reg *mreg, u32 reg, u32 val) +{ + struct mfis_priv *priv = mreg->priv; + u32 unprotect_mask = priv->info->unprotect_mask; + unsigned long flags; + u32 unprotect_code; + + /* + * [Gen4] key: 0xACCE0000, mask: 0x0000FFFF + * [Gen5] key: 0xACC00000, mask: 0x000FFFFF + */ + unprotect_code = (MFIS_UNPROTECT_KEY & ~unprotect_mask) | + ((mreg->start + reg) & unprotect_mask); + + spin_lock_irqsave(&priv->unprotect_lock, flags); + iowrite32(unprotect_code, priv->common_reg.base + MFISWACNTR); + iowrite32(val, mreg->base + reg); + spin_unlock_irqrestore(&priv->unprotect_lock, flags); +} + +/******************************************************** + * Mailbox * + ********************************************************/ + +#define mfis_mb_mbox_to_priv(_m) container_of((_m), struct mfis_priv, mbox) + +static irqreturn_t mfis_mb_iicr_interrupt(int irq, void *data) +{ + struct mbox_chan *chan = data; + struct mfis_priv *priv = mfis_mb_mbox_to_priv(chan->mbox); + struct mfis_chan_priv *chan_priv = chan->con_priv; + + mbox_chan_received_data(chan, NULL); + /* Stop remote(!) doorbell */ + mfis_write(&priv->mbox_reg, chan_priv->reg, 0); + + return IRQ_HANDLED; +} + +static int mfis_mb_startup(struct mbox_chan *chan) +{ + struct mfis_chan_priv *chan_priv = chan->con_priv; + + if (!chan_priv->irq) + return 0; + + return request_irq(chan_priv->irq, mfis_mb_iicr_interrupt, 0, + dev_name(chan->mbox->dev), chan); +} + +static void mfis_mb_shutdown(struct mbox_chan *chan) +{ + struct mfis_chan_priv *chan_priv = chan->con_priv; + + if (chan_priv->irq) + free_irq(chan_priv->irq, chan); +} + +static int mfis_mb_iicr_send_data(struct mbox_chan *chan, void *data) +{ + struct mfis_priv *priv = mfis_mb_mbox_to_priv(chan->mbox); + struct mfis_chan_priv *chan_priv = chan->con_priv; + + /* Our doorbell still active? */ + if (mfis_read(&priv->mbox_reg, chan_priv->reg) & BIT(0)) + return -EBUSY; + + /* Start our doorbell */ + mfis_write(&priv->mbox_reg, chan_priv->reg, BIT(0)); + + return 0; +} + +static bool mfis_mb_iicr_last_tx_done(struct mbox_chan *chan) +{ + struct mfis_priv *priv = mfis_mb_mbox_to_priv(chan->mbox); + struct mfis_chan_priv *chan_priv = chan->con_priv; + + /* Our doorbell still active? */ + return !(mfis_read(&priv->mbox_reg, chan_priv->reg) & BIT(0)); +} + +/* For MFIS variants using the IICR/EICR register pair */ +static const struct mbox_chan_ops mfis_iicr_ops = { + .startup = mfis_mb_startup, + .shutdown = mfis_mb_shutdown, + .send_data = mfis_mb_iicr_send_data, + .last_tx_done = mfis_mb_iicr_last_tx_done, +}; + +static struct mbox_chan *mfis_mb_of_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + struct mfis_priv *priv = mfis_mb_mbox_to_priv(mbox); + struct mfis_chan_priv *chan_priv; + bool tx_uses_eicr, is_only_rx; + u32 chan_num, chan_flags; + struct mbox_chan *chan; + + if (sp->args_count != 2) + return ERR_PTR(-EINVAL); + + chan_num = sp->args[0]; + chan_flags = sp->args[1]; + + if (chan_num >= priv->info->mb_num_channels) + return ERR_PTR(-EINVAL); + + /* Channel layout is described in mfis_mb_probe() */ + if (priv->info->mb_channels_are_unidir) { + is_only_rx = chan_flags & MFIS_CHANNEL_RX; + chan = mbox->chans + 2 * chan_num + is_only_rx; + } else { + is_only_rx = false; + chan = mbox->chans + chan_num; + } + + if (priv->info->mb_reg_comes_from_dt) { + tx_uses_eicr = chan_flags & MFIS_CHANNEL_EICR; + if (tx_uses_eicr) + chan += mbox->num_chans / 2; + } else { + tx_uses_eicr = priv->info->mb_tx_uses_eicr; + } + + chan_priv = chan->con_priv; + chan_priv->reg = (tx_uses_eicr ^ is_only_rx) ? MFIS_X5H_EICR(chan_num) : + MFIS_X5H_IICR(chan_num); + + if (!priv->info->mb_channels_are_unidir || is_only_rx) { + char irqname[8]; + char suffix = tx_uses_eicr ? 'i' : 'e'; + + /* "ch0i" or "ch0e" */ + scnprintf(irqname, sizeof(irqname), "ch%u%c", chan_num, suffix); + + chan_priv->irq = of_irq_get_byname(mbox->dev->of_node, irqname); + if (chan_priv->irq < 0) + return ERR_PTR(chan_priv->irq); + if (chan_priv->irq == 0) + return ERR_PTR(-ENOENT); + } + + return chan; +} + +static int mfis_mb_probe(struct mfis_priv *priv) +{ + unsigned int num_chan = priv->info->mb_num_channels; + struct device *dev = priv->dev; + struct mbox_controller *mbox; + struct mbox_chan *chan; + + if (priv->info->mb_channels_are_unidir) { + /* Channel layout: Ch0-TX, Ch0-RX, Ch1-TX... */ + num_chan *= 2; + } + + if (priv->info->mb_reg_comes_from_dt) { + /* Channel layout: <n> IICR channels, <n> EICR channels */ + num_chan *= 2; + } + + chan = devm_kcalloc(dev, num_chan, sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + priv->chan_privs = devm_kcalloc(dev, num_chan, sizeof(*priv->chan_privs), + GFP_KERNEL); + if (!priv->chan_privs) + return -ENOMEM; + + mbox = &priv->mbox; + + for (unsigned int i = 0; i < num_chan; i++) + chan[i].con_priv = &priv->chan_privs[i]; + + mbox->chans = chan; + mbox->num_chans = num_chan; + mbox->txdone_poll = true; + mbox->ops = &mfis_iicr_ops; + mbox->dev = dev; + mbox->of_xlate = mfis_mb_of_xlate; + + return devm_mbox_controller_register(dev, mbox); +} + +/******************************************************** + * Common * + ********************************************************/ +static int mfis_reg_probe(struct platform_device *pdev, struct mfis_priv *priv, + struct mfis_reg *mreg, const char *name, bool required) +{ + struct resource *res; + void __iomem *base; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); + + /* If there is no mailbox resource, registers are in the common space */ + if (!res && !required) { + *mreg = priv->common_reg; + } else { + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + mreg->base = base; + mreg->start = res->start; + mreg->priv = priv; + } + + return 0; +} + +static int mfis_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mfis_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->info = of_device_get_match_data(dev); + if (!priv->info) + return -ENOENT; + + spin_lock_init(&priv->unprotect_lock); + + ret = mfis_reg_probe(pdev, priv, &priv->common_reg, "common", true); + if (ret) + return ret; + + ret = mfis_reg_probe(pdev, priv, &priv->mbox_reg, "mboxes", false); + if (ret) + return ret; + + return mfis_mb_probe(priv); +} + +static const struct mfis_info mfis_info_r8a78000 = { + .unprotect_mask = 0x000fffff, + .mb_num_channels = 64, + .mb_reg_comes_from_dt = true, + .mb_channels_are_unidir = true, +}; + +static const struct mfis_info mfis_info_r8a78000_scp = { + .unprotect_mask = 0x000fffff, + .mb_num_channels = 32, + .mb_tx_uses_eicr = true, + .mb_channels_are_unidir = true, +}; + +static const struct of_device_id mfis_mfd_of_match[] = { + { .compatible = "renesas,r8a78000-mfis", .data = &mfis_info_r8a78000, }, + { .compatible = "renesas,r8a78000-mfis-scp", .data = &mfis_info_r8a78000_scp, }, + {} +}; +MODULE_DEVICE_TABLE(of, mfis_mfd_of_match); + +static struct platform_driver mfis_driver = { + .driver = { + .name = "rcar-mfis", + .of_match_table = mfis_mfd_of_match, + .suppress_bind_attrs = true, + }, + .probe = mfis_probe, +}; +module_platform_driver(mfis_driver); + +MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); +MODULE_AUTHOR("Wolfram Sang <wsa+renesas@sang-engineering.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Renesas R-Car MFIS driver"); diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 38ff0b823bdaf..dedb2a0be5864 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -442,8 +442,14 @@ static const struct renesas_id id_prr __initconst = { .mask = 0xff00, }; +static const struct renesas_id id_mfis __initconst = { + .offset = 0x44, + .mask = 0xff00, +}; + static const struct of_device_id renesas_ids[] __initconst = { { .compatible = "renesas,bsid", .data = &id_bsid }, + { .compatible = "renesas,r8a78000-mfis", .data = &id_mfis }, { .compatible = "renesas,r9a07g043-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l }, @@ -468,7 +474,7 @@ static int __init renesas_soc_init(void) const char *soc_id; int ret; - match = of_match_node(renesas_socs, of_root); + match = of_machine_get_match(renesas_socs); if (!match) return -ENODEV; @@ -501,7 +507,7 @@ static int __init renesas_soc_init(void) product = readl(chipid + id->offset); iounmap(chipid); - if (id == &id_prr) { + if (id == &id_prr || id == &id_mfis) { /* R-Car M3-W ES1.1 incorrectly identifies as ES2.0 */ if ((product & 0x7fff) == 0x5210) product ^= 0x11; diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h index 655440a3e7c68..028ecef81451c 100644 --- a/include/dt-bindings/clock/r8a73a4-clock.h +++ b/include/dt-bindings/clock/r8a73a4-clock.h @@ -23,6 +23,8 @@ #define R8A73A4_CLK_ZX 13 #define R8A73A4_CLK_ZS 14 #define R8A73A4_CLK_HP 15 +#define R8A73A4_CLK_ZTR 16 +#define R8A73A4_CLK_ZT 17 /* MSTP1 */ #define R8A73A4_CLK_TMU0 25 diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h index 1b3fdb39cc426..8a8816b2ff6ac 100644 --- a/include/dt-bindings/clock/r8a7740-clock.h +++ b/include/dt-bindings/clock/r8a7740-clock.h @@ -24,6 +24,8 @@ #define R8A7740_CLK_ZB 14 #define R8A7740_CLK_M3 15 #define R8A7740_CLK_CP 16 +#define R8A7740_CLK_ZTR 17 +#define R8A7740_CLK_ZT 18 /* MSTP1 */ #define R8A7740_CLK_CEU21 28 diff --git a/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h new file mode 100644 index 0000000000000..5ec5bfc27c7df --- /dev/null +++ b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G3L family pinctrl bindings. + * + * Copyright (C) 2026 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ +#define __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ + +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/* RZG3L_Px = Offset address of PFC_P_mn - 0x22 */ +#define RZG3L_P2 2 +#define RZG3L_P3 3 +#define RZG3L_P5 5 +#define RZG3L_P6 6 +#define RZG3L_P7 7 +#define RZG3L_P8 8 +#define RZG3L_PA 10 +#define RZG3L_PB 11 +#define RZG3L_PC 12 +#define RZG3L_PD 13 +#define RZG3L_PE 14 +#define RZG3L_PF 15 +#define RZG3L_PG 16 +#define RZG3L_PH 17 +#define RZG3L_PJ 19 +#define RZG3L_PK 20 +#define RZG3L_PL 21 +#define RZG3L_PM 22 +#define RZG3L_PS 28 + +#define RZG3L_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3L_P##b, p, f) +#define RZG3L_GPIO(port, pin) RZG2L_GPIO(RZG3L_P##port, pin) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ */ diff --git a/include/dt-bindings/soc/renesas,r8a78000-mfis.h b/include/dt-bindings/soc/renesas,r8a78000-mfis.h new file mode 100644 index 0000000000000..147a8aefc6438 --- /dev/null +++ b/include/dt-bindings/soc/renesas,r8a78000-mfis.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H +#define _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H + +/* + * Constants for the second mbox-cell of the Renesas MFIS IP core. To be treated + * as bit flags which can be ORed. + */ + +/* + * MFIS HW design before r8a78001 requires a channel to be marked as either + * TX or RX. + */ +#define MFIS_CHANNEL_TX (0 << 0) +#define MFIS_CHANNEL_RX (1 << 0) + +/* + * MFIS variants before r8a78001 work with pairs of IICR and EICR registers. + * Usually, it is specified in the datasheets which of the two a specific core + * should use. Then, it does not need extra description in DT. For plain MFIS + * of r8a78000, this is selectable, though. According to the system design and + * the firmware in use, these channels need to be marked. This is not needed + * with other versions of the MFIS, not even with MFIS-SCP of r8a78000. + */ +#define MFIS_CHANNEL_IICR (0 << 1) +#define MFIS_CHANNEL_EICR (1 << 1) + +#endif /* _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H */ diff --git a/include/linux/fsl/mc.h b/include/linux/fsl/mc.h index 1da63f2d70401..9f671e87c80c0 100644 --- a/include/linux/fsl/mc.h +++ b/include/linux/fsl/mc.h @@ -357,9 +357,11 @@ int mc_send_command(struct fsl_mc_io *mc_io, struct fsl_mc_command *cmd); #ifdef CONFIG_FSL_MC_BUS #define dev_is_fsl_mc(_dev) ((_dev)->bus == &fsl_mc_bus_type) +u32 fsl_mc_get_msi_id(struct device *dev); #else /* If fsl-mc bus is not present device cannot belong to fsl-mc bus */ #define dev_is_fsl_mc(_dev) (0) +#define fsl_mc_get_msi_id(_dev) (0) #endif /* Macro to check if a device is a container device */ @@ -419,10 +421,6 @@ int __must_check fsl_mc_object_allocate(struct fsl_mc_device *mc_dev, void fsl_mc_object_free(struct fsl_mc_device *mc_adev); -struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, - struct msi_domain_info *info, - struct irq_domain *parent); - int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev); void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev); diff --git a/include/linux/irqdomain_defs.h b/include/linux/irqdomain_defs.h index 36653e2ee1c92..3a03bdfeeee93 100644 --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h @@ -17,7 +17,6 @@ enum irq_domain_bus_token { DOMAIN_BUS_PLATFORM_MSI, DOMAIN_BUS_NEXUS, DOMAIN_BUS_IPI, - DOMAIN_BUS_FSL_MC_MSI, DOMAIN_BUS_TI_SCI_INTA_MSI, DOMAIN_BUS_WAKEUP, DOMAIN_BUS_VMD_MSI, diff --git a/include/uapi/linux/fsl_hypervisor.h b/include/uapi/linux/fsl_hypervisor.h index 1e237fba951fe..ab4388441e80c 100644 --- a/include/uapi/linux/fsl_hypervisor.h +++ b/include/uapi/linux/fsl_hypervisor.h @@ -114,9 +114,9 @@ struct fsl_hv_ioctl_stop { * @target: the partition ID of the target partition, or -1 for this * partition * @reserved: reserved, must be set to 0 - * @local_addr: user-space virtual address of a buffer in the local + * @local_vaddr: user-space virtual address of a buffer in the local * partition - * @remote_addr: guest physical address of a buffer in the + * @remote_paddr: guest physical address of a buffer in the * remote partition * @count: the number of bytes to copy. Both the local and remote * buffers must be at least 'count' bytes long |