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authorWei Fang <wei.fang@nxp.com>2026-05-18 16:25:01 +0800
committerPaolo Abeni <pabeni@redhat.com>2026-05-21 13:04:42 +0200
commit187fbae024c8439533d7f075f4ab4b594dc19992 (patch)
treee321ac024bddb5ae155be439cdbf1b10a705ffb0 /MAINTAINERS
parent0850005c26d2623f3d77489cf27d342191a97b5c (diff)
downloadlinux-next-history-187fbae024c8439533d7f075f4ab4b594dc19992.tar.gz
net: dsa: netc: introduce NXP NETC switch driver for i.MX94
For i.MX94 series, the NETC IP provides full 802.1Q Ethernet switch functionality, advanced QoS with 8 traffic classes, and a full range of TSN standards capabilities. The switch has 3 user ports and 1 CPU port, the CPU port is connected to an internal ENETC. Since the switch and the internal ENETC are fully integrated within the NETC IP, no back-to-back MAC connection is required. Instead, a light-weight "pseudo MAC" is used between the switch and the ENETC. This translates to lower power (less logic and memory) and lower delay (as there is no serialization delay across this link). Introduce the initial NETC switch driver with basic probe and remove functionality. More features will be added in subsequent patches. Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260518082506.1318236-11-wei.fang@nxp.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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diff --git a/MAINTAINERS b/MAINTAINERS
index ba0200c48b052..3e8adb27f3278 100644
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+++ b/MAINTAINERS
@@ -19301,6 +19301,17 @@ F: Documentation/devicetree/bindings/clock/*imx*
F: drivers/clk/imx/
F: include/dt-bindings/clock/*imx*
+NXP NETC ETHERNET SWITCH DRIVER
+M: Wei Fang <wei.fang@nxp.com>
+R: Clark Wang <xiaoning.wang@nxp.com>
+L: imx@lists.linux.dev
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml
+F: drivers/net/dsa/netc/
+F: include/linux/dsa/tag_netc.h
+F: net/dsa/tag_netc.c
+
NXP NETC TIMER PTP CLOCK DRIVER
M: Wei Fang <wei.fang@nxp.com>
M: Clark Wang <xiaoning.wang@nxp.com>