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authorMark Brown <broonie@kernel.org>2026-05-29 18:09:03 +0100
committerMark Brown <broonie@kernel.org>2026-05-29 18:09:03 +0100
commit1468c70a92378ec85d66fce71a533d4bee6ed8cd (patch)
treef7ae0e67f2b3cc81a01a4ccfa472e1cf006508d8 /arch
parent636537b990be485724c0965ceb848e7e311e0254 (diff)
parentd6c3060f8c5df453d92216fcf629a23ee0852d37 (diff)
downloadlinux-next-history-1468c70a92378ec85d66fce71a533d4bee6ed8cd.tar.gz
Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi1439
-rw-r--r--arch/arm/boot/dts/nvidia/tegra114.dtsi157
-rw-r--r--arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi5
-rw-r--r--arch/arm/boot/dts/nvidia/tegra124-venice2.dts5
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra132-norrin.dts5
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194.dtsi9
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-smaug.dts7
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra234.dtsi24
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts12
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra264.dtsi88
10 files changed, 1703 insertions, 48 deletions
diff --git a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
new file mode 100644
index 0000000000000..bab6122dba48d
--- /dev/null
+++ b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
@@ -0,0 +1,1439 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ core_opp_table: opp-table-core {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ core_opp_900: opp-900000 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-level = <900000>;
+ };
+
+ core_opp_950: opp-950000 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-level = <950000>;
+ };
+
+ core_opp_1000: opp-1000000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-level = <1000000>;
+ };
+
+ core_opp_1050: opp-1050000 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-level = <1050000>;
+ };
+
+ core_opp_1100: opp-1100000 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-level = <1100000>;
+ };
+
+ core_opp_1120: opp-1120000 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-level = <1120000>;
+ };
+
+ core_opp_1150: opp-1150000 {
+ opp-microvolt = <1150000 1150000 1390000>;
+ opp-level = <1150000>;
+ };
+
+ core_opp_1170: opp-1170000 {
+ opp-microvolt = <1170000 1170000 1390000>;
+ opp-level = <1170000>;
+ };
+
+ core_opp_1200: opp-1200000 {
+ opp-microvolt = <1200000 1200000 1390000>;
+ opp-level = <1200000>;
+ };
+
+ core_opp_1250: opp-1250000 {
+ opp-microvolt = <1250000 1250000 1390000>;
+ opp-level = <1250000>;
+ };
+
+ core_opp_1300: opp-1300000 {
+ opp-microvolt = <1300000 1300000 1390000>;
+ opp-level = <1300000>;
+ };
+
+ core_opp_1350: opp-1350000 {
+ opp-microvolt = <1350000 1350000 1390000>;
+ opp-level = <1350000>;
+ };
+
+ core_opp_1390: opp-1390000 {
+ opp-microvolt = <1390000 1390000 1390000>;
+ opp-level = <1390000>;
+ };
+ };
+
+ emc_icc_dvfs_opp_table: opp-table-emc {
+ compatible = "operating-points-v2";
+
+ opp-12750000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <12750000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-20400000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <20400000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-40800000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <40800000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-68000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <68000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-102000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <102000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-204000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <204000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ opp-suspend;
+ };
+
+ opp-312000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <312000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-408000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ /*
+ * T40X can work with 1050mV for 528MHz but T40T which is
+ * in the same group as T40X requires 1100mV. If there will
+ * be enough data that T40T can work reliably with 1050mV
+ * for 528MHz then voltage for 528MHz opp can be lowered.
+ * T40S should remain with 1100mV for 528MHz opp.
+ */
+ opp-528000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <528000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-624000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <624000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-792000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <792000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-900000000-1200 {
+ opp-microvolt = <1200000 1200000 1390000>;
+ opp-hz = /bits/ 64 <900000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1200>;
+ };
+ };
+
+ emc_bw_dfs_opp_table: opp-table-actmon {
+ compatible = "operating-points-v2";
+
+ opp-12750000 {
+ opp-hz = /bits/ 64 <12750000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <204000>;
+ };
+
+ opp-20400000 {
+ opp-hz = /bits/ 64 <20400000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <326400>;
+ };
+
+ opp-40800000 {
+ opp-hz = /bits/ 64 <40800000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <652800>;
+ };
+
+ opp-68000000 {
+ opp-hz = /bits/ 64 <68000000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <1088000>;
+ };
+
+ opp-102000000 {
+ opp-hz = /bits/ 64 <102000000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <1632000>;
+ };
+
+ opp-204000000 {
+ opp-hz = /bits/ 64 <204000000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <3264000>;
+ opp-suspend;
+ };
+
+ opp-312000000 {
+ opp-hz = /bits/ 64 <312000000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <4992000>;
+ };
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <6528000>;
+ };
+
+ opp-528000000 {
+ opp-hz = /bits/ 64 <528000000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <8448000>;
+ };
+
+ opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <9984000>;
+ };
+
+ opp-792000000 {
+ opp-hz = /bits/ 64 <792000000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <12672000>;
+ };
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-supported-hw = <0x000E>;
+ opp-peak-kBps = <14400000>;
+ };
+ };
+
+ vi_dvfs_opp_table: opp-table-vi {
+ compatible = "operating-points-v2";
+
+ opp-114000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <114000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-216000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <216000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-240000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <240000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-312000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <312000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-372000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <372000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-408000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-408000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1120>;
+ };
+ };
+
+ epp_dvfs_opp_table: opp-table-epp {
+ compatible = "operating-points-v2";
+
+ opp-192000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <192000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-240000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <240000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-228000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <228000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-300000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-300000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-384000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <384000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-396000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <396000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-468000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <468000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-492000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <492000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-528000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <528000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-516000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <516000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-564000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <564000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-552000000-1170 {
+ opp-microvolt = <1170000 1170000 1390000>;
+ opp-hz = /bits/ 64 <552000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1170>;
+ };
+
+ opp-600000000-1170 {
+ opp-microvolt = <1170000 1170000 1390000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1170>;
+ };
+
+ opp-600000000-1250 {
+ opp-microvolt = <1250000 1250000 1390000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp-636000000-1200 {
+ opp-microvolt = <1200000 1200000 1390000>;
+ opp-hz = /bits/ 64 <636000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp-672000000-1250 {
+ opp-microvolt = <1250000 1250000 1390000>;
+ opp-hz = /bits/ 64 <672000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp-828000000-1390 {
+ opp-microvolt = <1390000 1390000 1390000>;
+ opp-hz = /bits/ 64 <828000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1390>;
+ };
+ };
+
+ gr2d_dvfs_opp_table: opp-table-gr2d {
+ compatible = "operating-points-v2";
+
+ opp-192000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <192000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-240000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <240000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-228000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <228000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-300000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-300000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-384000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <384000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-396000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <396000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-468000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <468000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-492000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <492000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-528000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <528000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-516000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <516000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-564000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <564000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-552000000-1170 {
+ opp-microvolt = <1170000 1170000 1390000>;
+ opp-hz = /bits/ 64 <552000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1170>;
+ };
+
+ opp-600000000-1170 {
+ opp-microvolt = <1170000 1170000 1390000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1170>;
+ };
+
+ opp-600000000-1250 {
+ opp-microvolt = <1250000 1250000 1390000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp-636000000-1200 {
+ opp-microvolt = <1200000 1200000 1390000>;
+ opp-hz = /bits/ 64 <636000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp-672000000-1250 {
+ opp-microvolt = <1250000 1250000 1390000>;
+ opp-hz = /bits/ 64 <672000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp-828000000-1390 {
+ opp-microvolt = <1390000 1390000 1390000>;
+ opp-hz = /bits/ 64 <828000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1390>;
+ };
+ };
+
+ gr3d_dvfs_opp_table: opp-table-gr3d {
+ compatible = "operating-points-v2";
+
+ opp-192000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <192000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-240000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <240000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-228000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <228000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-300000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-300000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-384000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <384000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-396000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <396000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-468000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <468000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-492000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <492000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-528000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <528000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-516000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <516000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-564000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <564000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-552000000-1170 {
+ opp-microvolt = <1170000 1170000 1390000>;
+ opp-hz = /bits/ 64 <552000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1170>;
+ };
+
+ opp-600000000-1170 {
+ opp-microvolt = <1170000 1170000 1390000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1170>;
+ };
+
+ opp-600000000-1250 {
+ opp-microvolt = <1250000 1250000 1390000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp-636000000-1200 {
+ opp-microvolt = <1200000 1200000 1390000>;
+ opp-hz = /bits/ 64 <636000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp-672000000-1250 {
+ opp-microvolt = <1250000 1250000 1390000>;
+ opp-hz = /bits/ 64 <672000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp-828000000-1390 {
+ opp-microvolt = <1390000 1390000 1390000>;
+ opp-hz = /bits/ 64 <828000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1390>;
+ };
+ };
+
+ msenc_dvfs_opp_table: opp-table-msenc {
+ compatible = "operating-points-v2";
+
+ opp-144000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <144000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-182000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <182000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-204000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <204000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-240000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <240000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-252000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <252000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-312000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <312000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-324000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <324000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-384000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <384000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-408000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-432000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <432000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-456000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <456000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-480000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-480000000-1170 {
+ opp-microvolt = <1170000 1170000 1390000>;
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1170>;
+ };
+ };
+
+ tsec_dvfs_opp_table: opp-table-tsec {
+ compatible = "operating-points-v2";
+
+ opp-144000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <144000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-182000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <182000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-204000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <204000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-240000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <240000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-252000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <252000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-312000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <312000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-324000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <324000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-384000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <384000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-408000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-432000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <432000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-456000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <456000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-480000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-480000000-1170 {
+ opp-microvolt = <1170000 1170000 1390000>;
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1170>;
+ };
+ };
+
+ vde_dvfs_opp_table: opp-table-vde {
+ compatible = "operating-points-v2";
+
+ opp-144000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <144000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-182000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <182000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-204000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <204000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-240000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <240000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-252000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <252000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-312000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <312000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-324000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <324000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-384000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <384000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-408000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-432000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <432000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-456000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <456000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-480000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-480000000-1170 {
+ opp-microvolt = <1170000 1170000 1390000>;
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1170>;
+ };
+ };
+
+ host1x_dvfs_opp_table: opp-table-host1x {
+ compatible = "operating-points-v2";
+
+ opp-144000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <144000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-180000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <180000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-188000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <188000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-228000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <228000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-240000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <240000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-276000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <276000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-276000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <276000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-324000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <324000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-336000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <336000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp-336000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <336000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-372000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <372000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp-384000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <384000000>;
+ opp-supported-hw = <0x000E>;
+ required-opps = <&core_opp_1120>;
+ };
+ };
+
+ pll_m_dvfs_opp_table: opp-table-pllm {
+ compatible = "operating-points-v2";
+
+ opp-800000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <800000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-1066000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <1066000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ pll_c_dvfs_opp_table: opp-table-pllc {
+ compatible = "operating-points-v2";
+
+ opp-800000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <800000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-1066000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <1066000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ pll_c2_dvfs_opp_table: opp-table-pllc2 {
+ compatible = "operating-points-v2";
+
+ opp-800000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <800000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-1066000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <1066000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ pll_c3_dvfs_opp_table: opp-table-pllc3 {
+ compatible = "operating-points-v2";
+
+ opp-800000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <800000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-1066000000-1000 {
+ opp-microvolt = <1000000 1000000 1390000>;
+ opp-hz = /bits/ 64 <1066000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ sbc1_dvfs_opp_table: opp-table-sbc1 {
+ compatible = "operating-points-v2";
+
+ opp-48000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <48000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-52000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1100>;
+ };
+ };
+
+ sbc2_dvfs_opp_table: opp-table-sbc2 {
+ compatible = "operating-points-v2";
+
+ opp-48000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <48000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-52000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1100>;
+ };
+ };
+
+ sbc3_dvfs_opp_table: opp-table-sbc3 {
+ compatible = "operating-points-v2";
+
+ opp-48000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <48000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-52000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1100>;
+ };
+ };
+
+ sbc4_dvfs_opp_table: opp-table-sbc4 {
+ compatible = "operating-points-v2";
+
+ opp-48000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <48000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-52000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1100>;
+ };
+ };
+
+ sbc5_dvfs_opp_table: opp-table-sbc5 {
+ compatible = "operating-points-v2";
+
+ opp-48000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <48000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-52000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1100>;
+ };
+ };
+
+ sbc6_dvfs_opp_table: opp-table-sbc6 {
+ compatible = "operating-points-v2";
+
+ opp-48000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <48000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-52000000-1100 {
+ opp-microvolt = <1100000 1100000 1390000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1100>;
+ };
+ };
+
+ sdmmc1_dvfs_opp_table: opp-table-sdmmc1 {
+ compatible = "operating-points-v2";
+
+ opp-81600000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <81600000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-156000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <156000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-204000000-1250 {
+ opp-microvolt = <1250000 1250000 1390000>;
+ opp-hz = /bits/ 64 <204000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1250>;
+ };
+ };
+
+ sdmmc3_dvfs_opp_table: opp-table-sdmmc3 {
+ compatible = "operating-points-v2";
+
+ opp-81600000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <81600000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-156000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <156000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-204000000-1250 {
+ opp-microvolt = <1250000 1250000 1390000>;
+ opp-hz = /bits/ 64 <204000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1250>;
+ };
+ };
+
+ sdmmc4_dvfs_opp_table: opp-table-sdmmc4 {
+ compatible = "operating-points-v2";
+
+ opp-81600000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <81600000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp-156000000-1120 {
+ opp-microvolt = <1120000 1120000 1390000>;
+ opp-hz = /bits/ 64 <156000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1120>;
+ };
+
+ opp-200000000-1250 {
+ opp-microvolt = <1250000 1250000 1390000>;
+ opp-hz = /bits/ 64 <200000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1250>;
+ };
+ };
+
+ hdmi_dvfs_opp_table: opp-table-hdmi {
+ compatible = "operating-points-v2";
+
+ opp-148500000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <148500000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-297000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <297000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1050>;
+ };
+ };
+
+ disp1_dvfs_opp_table: opp-table-disp1 {
+ compatible = "operating-points-v2";
+
+ opp-166000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <166000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-297000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <297000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1050>;
+ };
+ };
+
+ disp2_dvfs_opp_table: opp-table-disp2 {
+ compatible = "operating-points-v2";
+
+ opp-166000000-900 {
+ opp-microvolt = <900000 900000 1390000>;
+ opp-hz = /bits/ 64 <166000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_900>;
+ };
+
+ opp-297000000-1050 {
+ opp-microvolt = <1050000 1050000 1390000>;
+ opp-hz = /bits/ 64 <297000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1050>;
+ };
+ };
+
+ xusb_falcon_dvfs_opp_table: opp-table-xusb-falcon {
+ compatible = "operating-points-v2";
+
+ opp-336000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <336000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+ };
+
+ xusb_host_dvfs_opp_table: opp-table-xusb-host {
+ compatible = "operating-points-v2";
+
+ opp-112000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <112000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+ };
+
+ xusb_dev_dvfs_opp_table: opp-table-xusb-dev {
+ compatible = "operating-points-v2";
+
+ opp-58300000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <58300000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+ };
+
+ xusb_ss_dvfs_opp_table: opp-table-xusb-ss {
+ compatible = "operating-points-v2";
+
+ opp-122400000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <122400000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+ };
+
+ xusb_fs_dvfs_opp_table: opp-table-xusb-fs {
+ compatible = "operating-points-v2";
+
+ opp-48000000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <48000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+ };
+
+ xusb_hs_dvfs_opp_table: opp-table-xusb-hs {
+ compatible = "operating-points-v2";
+
+ opp-61200000-950 {
+ opp-microvolt = <950000 950000 1390000>;
+ opp-hz = /bits/ 64 <61200000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+ };
+
+ /* Add usbd, usb2 and usb3 opp tables if needed */
+};
diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index 7e8f90d339359..a5958f3a965b2 100644
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/soc/tegra-pmc.h>
#include <dt-bindings/thermal/tegra114-soctherm.h>
+#include "tegra114-peripherals-opp.dtsi"
+
/ {
compatible = "nvidia,tegra114";
interrupt-parent = <&lic>;
@@ -56,6 +58,8 @@
clocks = <&tegra_car TEGRA114_CLK_VI>;
resets = <&tegra_car 20>;
reset-names = "vi";
+ power-domains = <&pd_venc>;
+ operating-points-v2 = <&vi_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_VI>;
@@ -69,6 +73,8 @@
clocks = <&tegra_car TEGRA114_CLK_EPP>;
resets = <&tegra_car TEGRA114_CLK_EPP>;
reset-names = "epp";
+ power-domains = <&pd_heg>;
+ operating-points-v2 = <&epp_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_EPP>;
@@ -82,6 +88,7 @@
clocks = <&tegra_car TEGRA114_CLK_ISP>;
resets = <&tegra_car TEGRA114_CLK_ISP>;
reset-names = "isp";
+ power-domains = <&pd_venc>;
iommus = <&mc TEGRA_SWGROUP_ISP>;
@@ -95,6 +102,8 @@
clocks = <&tegra_car TEGRA114_CLK_GR2D>;
resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>;
reset-names = "2d", "mc";
+ power-domains = <&pd_heg>;
+ operating-points-v2 = <&gr2d_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_G2>;
};
@@ -105,6 +114,8 @@
clocks = <&tegra_car TEGRA114_CLK_GR3D>;
resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>;
reset-names = "3d", "mc";
+ power-domains = <&pd_3d>;
+ operating-points-v2 = <&gr3d_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_NV>;
};
@@ -118,11 +129,24 @@
clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&disp1_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_DC>;
nvidia,head = <0>;
+ interconnects = <&mc TEGRA114_MC_DISPLAY0A &emc>,
+ <&mc TEGRA114_MC_DISPLAY0B &emc>,
+ <&mc TEGRA114_MC_DISPLAY1B &emc>,
+ <&mc TEGRA114_MC_DISPLAY0C &emc>,
+ <&mc TEGRA114_MC_DISPLAYHC &emc>;
+ interconnect-names = "wina",
+ "winb",
+ "winb-vfilter",
+ "winc",
+ "cursor";
+
rgb {
status = "disabled";
};
@@ -137,11 +161,24 @@
clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&disp2_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_DCB>;
nvidia,head = <1>;
+ interconnects = <&mc TEGRA114_MC_DISPLAY0AB &emc>,
+ <&mc TEGRA114_MC_DISPLAY0BB &emc>,
+ <&mc TEGRA114_MC_DISPLAY1BB &emc>,
+ <&mc TEGRA114_MC_DISPLAY0CB &emc>,
+ <&mc TEGRA114_MC_DISPLAYHCB &emc>;
+ interconnect-names = "wina",
+ "winb",
+ "winb-vfilter",
+ "winc",
+ "cursor";
+
rgb {
status = "disabled";
};
@@ -156,6 +193,8 @@
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&hdmi_dvfs_opp_table>;
status = "disabled";
};
@@ -169,6 +208,7 @@
resets = <&tegra_car 48>;
reset-names = "dsi";
nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
+ power-domains = <&pd_core>;
status = "disabled";
#address-cells = <1>;
@@ -185,6 +225,7 @@
resets = <&tegra_car 82>;
reset-names = "dsi";
nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
+ power-domains = <&pd_core>;
status = "disabled";
#address-cells = <1>;
@@ -198,6 +239,8 @@
clocks = <&tegra_car TEGRA114_CLK_MSENC>;
resets = <&tegra_car TEGRA114_CLK_MSENC>;
reset-names = "mpe";
+ power-domains = <&pd_mpe>;
+ operating-points-v2 = <&msenc_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_MSENC>;
@@ -210,6 +253,8 @@
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_TSEC>;
resets = <&tegra_car TEGRA114_CLK_TSEC>;
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&tsec_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_TSEC>;
@@ -323,6 +368,9 @@
clock-names = "actmon", "emc";
resets = <&tegra_car TEGRA114_CLK_ACTMON>;
reset-names = "actmon";
+ operating-points-v2 = <&emc_bw_dfs_opp_table>;
+ interconnects = <&mc TEGRA114_MC_MPCORER &emc>;
+ interconnect-names = "cpu-read";
#cooling-cells = <2>;
};
@@ -366,6 +414,8 @@
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>;
iommus = <&mc TEGRA_SWGROUP_VDE>;
+ power-domains = <&pd_vde>;
+ operating-points-v2 = <&vde_dvfs_opp_table>;
};
apbmisc@70000800 {
@@ -443,6 +493,7 @@
clocks = <&tegra_car TEGRA114_CLK_PWM>;
resets = <&tegra_car 17>;
reset-names = "pwm";
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -533,6 +584,8 @@
reset-names = "spi";
dmas = <&apbdma 15>, <&apbdma 15>;
dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&sbc1_dvfs_opp_table>;
status = "disabled";
};
@@ -548,6 +601,8 @@
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&sbc2_dvfs_opp_table>;
status = "disabled";
};
@@ -563,6 +618,8 @@
reset-names = "spi";
dmas = <&apbdma 17>, <&apbdma 17>;
dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&sbc3_dvfs_opp_table>;
status = "disabled";
};
@@ -578,6 +635,8 @@
reset-names = "spi";
dmas = <&apbdma 18>, <&apbdma 18>;
dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&sbc4_dvfs_opp_table>;
status = "disabled";
};
@@ -593,6 +652,8 @@
reset-names = "spi";
dmas = <&apbdma 27>, <&apbdma 27>;
dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&sbc5_dvfs_opp_table>;
status = "disabled";
};
@@ -608,6 +669,8 @@
reset-names = "spi";
dmas = <&apbdma 28>, <&apbdma 28>;
dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&sbc6_dvfs_opp_table>;
status = "disabled";
};
@@ -634,6 +697,86 @@
clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
+
+ pd_core: core-domain {
+ #power-domain-cells = <0>;
+ operating-points-v2 = <&core_opp_table>;
+ };
+
+ powergates {
+ /*
+ * TODO: Add DIS and DISB domains once DC is able
+ * to handle them properly. VENC and DISB should
+ * set DIS as their source power domain due to
+ * internal dependency.
+ */
+
+ pd_heg: heg {
+ clocks = <&tegra_car TEGRA114_CLK_GR2D>,
+ <&tegra_car TEGRA114_CLK_EPP>;
+ resets = <&mc TEGRA114_MC_RESET_2D>,
+ <&mc TEGRA114_MC_RESET_EPP>,
+ <&tegra_car TEGRA114_CLK_GR2D>,
+ <&tegra_car TEGRA114_CLK_EPP>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_mpe: mpe {
+ clocks = <&tegra_car TEGRA114_CLK_MSENC>;
+ resets = <&mc TEGRA114_MC_RESET_MPE>,
+ <&tegra_car TEGRA114_CLK_MSENC>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_3d: td {
+ clocks = <&tegra_car TEGRA114_CLK_GR3D>;
+ resets = <&mc TEGRA114_MC_RESET_3D>,
+ <&tegra_car TEGRA114_CLK_GR3D>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_vde: vdec {
+ clocks = <&tegra_car TEGRA114_CLK_VDE>;
+ resets = <&mc TEGRA114_MC_RESET_VDE>,
+ <&tegra_car TEGRA114_CLK_VDE>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_venc: venc {
+ clocks = <&tegra_car TEGRA114_CLK_ISP>,
+ <&tegra_car TEGRA114_CLK_VI>,
+ <&tegra_car TEGRA114_CLK_CSI>;
+ resets = <&mc TEGRA114_MC_RESET_ISP>,
+ <&mc TEGRA114_MC_RESET_VI>,
+ <&tegra_car TEGRA114_CLK_ISP>,
+ <&tegra_car 20 /* VI */>,
+ <&tegra_car TEGRA114_CLK_CSI>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_xusbss: xusba {
+ clocks = <&tegra_car TEGRA114_CLK_XUSB_SS>;
+ resets = <&tegra_car TEGRA114_CLK_XUSB_SS>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_xusbdev: xusbb {
+ clocks = <&tegra_car TEGRA114_CLK_XUSB_DEV>;
+ resets = <&tegra_car 95>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_xusbhost: xusbc {
+ clocks = <&tegra_car TEGRA114_CLK_XUSB_HOST>;
+ resets = <&tegra_car TEGRA114_CLK_XUSB_HOST>;
+ #power-domain-cells = <0>;
+ };
+ };
};
fuse@7000f800 {
@@ -643,6 +786,7 @@
clock-names = "fuse";
resets = <&tegra_car 39>;
reset-names = "fuse";
+ power-domains = <&pd_core>;
};
mc: memory-controller@70019000 {
@@ -655,6 +799,7 @@
#reset-cells = <1>;
#iommu-cells = <1>;
+ #interconnect-cells = <1>;
};
emc: external-memory-controller@7001b000 {
@@ -663,8 +808,12 @@
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_EMC>;
clock-names = "emc";
+ power-domains = <&pd_core>;
nvidia,memory-controller = <&mc>;
+ operating-points-v2 = <&emc_icc_dvfs_opp_table>;
+
+ #interconnect-cells = <0>;
};
hda@70030000 {
@@ -854,6 +1003,8 @@
clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
status = "disabled";
};
@@ -876,6 +1027,8 @@
clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
status = "disabled";
};
@@ -887,6 +1040,8 @@
clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&sdmmc4_dvfs_opp_table>;
status = "disabled";
};
@@ -899,6 +1054,7 @@
resets = <&tegra_car 22>;
reset-names = "usb";
nvidia,phy = <&phy1>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -939,6 +1095,7 @@
resets = <&tegra_car 59>;
reset-names = "usb";
nvidia,phy = <&phy3>;
+ power-domains = <&pd_core>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi
index 974c76f007db4..89a749cb89338 100644
--- a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi
@@ -14,6 +14,11 @@
stdout-path = "serial0:115200n8";
};
+ firmware {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
/*
* Note that recent version of the device tree compiler (starting with
* version 1.4.2) warn about this node containing a reg property, but
diff --git a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts
index df98dc2a67b85..059ee6c5b13cd 100644
--- a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts
@@ -18,6 +18,11 @@
stdout-path = "serial0:115200n8";
};
+ firmware {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
index 683ac124523b3..1f5222d43e62c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
@@ -18,6 +18,11 @@
stdout-path = "serial0:115200n8";
};
+ firmware {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 849694f751d90..7bbf0e892724d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -2382,6 +2382,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2434,6 +2435,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2486,6 +2488,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2538,6 +2541,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2583,6 +2587,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
@@ -2629,6 +2634,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2674,6 +2680,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
@@ -2723,6 +2730,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2771,6 +2779,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index f0b8c2c80aa50..e0fde65a552be 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -25,6 +25,11 @@
stdout-path = "serial0:115200n8";
};
+ firmware {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0xc0000000>;
@@ -1467,6 +1472,8 @@
gpio-controller;
#gpio-cells = <2>;
+ system-power-controller;
+
pinctrl-names = "default";
pinctrl-0 = <&max77620_default>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 04a95b6658caa..8e0c51e496e20 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -3605,7 +3605,7 @@
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
- clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
@@ -3647,7 +3647,7 @@
<&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
- clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
@@ -3689,7 +3689,7 @@
<&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
- clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
@@ -3731,7 +3731,7 @@
<&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
- clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
@@ -4532,6 +4532,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4586,6 +4587,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4640,6 +4642,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4686,6 +4689,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <32000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
@@ -4734,6 +4738,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4788,6 +4793,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4842,6 +4848,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4896,6 +4903,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4937,6 +4945,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <32000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
@@ -4983,6 +4992,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -5037,6 +5047,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -5083,6 +5094,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <32000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
@@ -5131,6 +5143,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -5177,6 +5190,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <32000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
@@ -5225,6 +5239,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -5271,6 +5286,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <32000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts
index df6555b6d0e0a..3bd4c4cf28714 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts
@@ -8,4 +8,16 @@
/ {
model = "NVIDIA Jetson AGX Thor Developer Kit";
compatible = "nvidia,p4071-0000+p3834-0008", "nvidia,p3834-0008", "nvidia,tegra264";
+
+ bus@a800000000 {
+ /* PCIe C2 to enable Ethernet */
+ pci@8420000 {
+ status = "okay";
+ };
+
+ /* PCIe C5 to enable NVME */
+ pci@8480000 {
+ status = "okay";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 06d8357bdf527..2d8e7e37830ff 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3277,50 +3277,6 @@
status = "disabled";
};
- gpio_main: gpio@c300000 {
- compatible = "nvidia,tegra264-gpio";
- reg = <0x00 0x0c300000 0x0 0x4000>,
- <0x00 0x0c310000 0x0 0x4000>;
- reg-names = "security", "gpio";
- wakeup-parent = <&pmc>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
serial@c4e0000 {
compatible = "nvidia,tegra264-utc";
reg = <0x0 0x0c4e0000 0x0 0x8000>,
@@ -3586,6 +3542,50 @@
status = "disabled";
};
+ gpio_main: gpio@c300000 {
+ compatible = "nvidia,tegra264-gpio";
+ reg = <0x00 0x0c300000 0x0 0x4000>,
+ <0x00 0x0c310000 0x0 0x4000>;
+ reg-names = "security", "gpio";
+ wakeup-parent = <&pmc>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
i2c14: i2c@c410000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c410000 0x0 0x10000>;
generated by cgit 1.3-korg (git 2.53.0) at 2026-06-01 04:07:25 +0000