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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-05-28 08:45:44 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-29 14:57:47 +0200 |
| commit | 32a88389a0bc00c196e621e32f6de0656ff1156b (patch) | |
| tree | 6a3e1b27837191ca355437aa6db2938c5c1a629f /arch | |
| parent | 52d7c11a0d586300b16028a64c8367c8bf75fc8e (diff) | |
| download | linux-next-history-32a88389a0bc00c196e621e32f6de0656ff1156b.tar.gz | |
arm64: dts: renesas: rzg3l-smarc-som: Enable Versa clock generator
The RZ/G3L SMARC SoM has a Versa 5P35023B clock generator to generate
the following clocks:
- ref: Not connected,
- se1: AUDIO_MCK (11.2896 or 12.2880 MHz),
- se2: RZ_AUDIO_CLK_B (11.2896 MHz),
- se3: RZ_AUDIO_CLK_C (12.2880 MHz),
- diff{1,1B}: ET{0,1}_PHY_CLK (25 MHz),
- diff2{2,2B}: Not connected.
Enable the Vversa 5P35023B clock generator on the RZ/G3L SoM DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260528074615.91110-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index 17bf447783988..5e58e08e7fada 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -40,6 +40,12 @@ /* First 128MiB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x78000000>; }; + + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; ð0 { @@ -75,6 +81,18 @@ &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x2_clk>; + + assigned-clocks = <&versa3 1>, <&versa3 2>, + <&versa3 3>, <&versa3 4>; + assigned-clock-rates = <12288000>, <11289600>, + <12288000>, <25000000>; + }; }; &mdio0 { |