diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2026-05-01 11:51:16 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-25 13:33:12 +0200 |
| commit | 9c8ee64dc70ba16aaefc240d4e2dfc0e53d293ad (patch) | |
| tree | 1096295e541c84ee04736221aabc6f0735fdd298 /arch | |
| parent | d95557d87f60c904b2f34995f7659645384279dc (diff) | |
| download | linux-next-history-9c8ee64dc70ba16aaefc240d4e2dfc0e53d293ad.tar.gz | |
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable PCIe
Enable the PCIE1 slot available on the RZ/V2N EVK.
Note, the PCIE_REFCLK comes from 5L35023B versa clock generator, once the
support for this clock generator is added, the fixed clock node can be
removed and can be replaced with a reference to the clock generator.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260501105116.33452-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 00e5455ea5abf..43ffde419d911 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -63,6 +63,12 @@ reg = <0x0 0x48000000 0x1 0xf8000000>; }; + pcie_refclk: clock-pcie-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_0p8v: regulator-0p8v { compatible = "regulator-fixed"; regulator-name = "fixed-0.8V"; @@ -333,6 +339,17 @@ status = "okay"; }; +&pcie { + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pcie_port0 { + clocks = <&pcie_refclk>; + clock-names = "ref"; +}; + &pinctrl { eth0_pins: eth0 { pins = "ET0_TXC_TXCLK"; @@ -383,6 +400,12 @@ <RZV2N_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */ }; + pcie_pins: pcie { + pins = "PCIE0_RSTOUTB"; + slew-rate = <0>; + renesas,output-impedance = <2>; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; |