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| author | Mark Brown <broonie@kernel.org> | 2026-05-29 18:09:20 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-05-29 18:09:20 +0100 |
| commit | c4a3570507e705aa00c1f71ba812ed5cea19709a (patch) | |
| tree | 969e06cd5e48c7a290bfd27a7a8e5fcbb1b43767 /arch | |
| parent | 87a99c228b30d35b92e91e05db6516d9fc78e962 (diff) | |
| parent | aca063c9024522e4e5b9a9d1927433f6a01785a3 (diff) | |
| download | linux-next-history-c4a3570507e705aa00c1f71ba812ed5cea19709a.tar.gz | |
Merge branch 'for-next' of https://github.com/openrisc/linux.git
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/openrisc/include/asm/cacheflush.h | 4 | ||||
| -rw-r--r-- | arch/openrisc/kernel/head.S | 10 | ||||
| -rw-r--r-- | arch/openrisc/kernel/jump_label.c | 2 | ||||
| -rw-r--r-- | arch/openrisc/kernel/patching.c | 3 | ||||
| -rw-r--r-- | arch/openrisc/kernel/smp.c | 21 | ||||
| -rw-r--r-- | arch/openrisc/mm/cache.c | 16 | ||||
| -rw-r--r-- | arch/openrisc/mm/init.c | 2 |
7 files changed, 46 insertions, 12 deletions
diff --git a/arch/openrisc/include/asm/cacheflush.h b/arch/openrisc/include/asm/cacheflush.h index cd8f971c0fecc..7b8c043a831df 100644 --- a/arch/openrisc/include/asm/cacheflush.h +++ b/arch/openrisc/include/asm/cacheflush.h @@ -26,6 +26,7 @@ extern void local_icache_page_inv(struct page *page); extern void local_dcache_range_flush(unsigned long start, unsigned long end); extern void local_dcache_range_inv(unsigned long start, unsigned long end); extern void local_icache_range_inv(unsigned long start, unsigned long end); +extern void local_icache_all_inv(void); /* * Data cache flushing always happen on the local cpu. Instruction cache @@ -35,10 +36,13 @@ extern void local_icache_range_inv(unsigned long start, unsigned long end); #ifndef CONFIG_SMP #define dcache_page_flush(page) local_dcache_page_flush(page) #define icache_page_inv(page) local_icache_page_inv(page) +#define icache_all_inv() local_icache_all_inv() #else /* CONFIG_SMP */ #define dcache_page_flush(page) local_dcache_page_flush(page) #define icache_page_inv(page) smp_icache_page_inv(page) +#define icache_all_inv() smp_icache_all_inv() extern void smp_icache_page_inv(struct page *page); +extern void smp_icache_all_inv(void); #endif /* CONFIG_SMP */ /* diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S index 45890393947d8..d5befd632fa9e 100644 --- a/arch/openrisc/kernel/head.S +++ b/arch/openrisc/kernel/head.S @@ -852,26 +852,19 @@ _ic_enable: l.sll r14,r30,r28 /* Establish number of cache sets - r16 contains number of cache sets r28 contains log(# of cache sets) */ l.andi r26,r24,SPR_ICCFGR_NCS l.srli r28,r26,3 - l.ori r30,r0,1 - l.sll r16,r30,r28 /* Invalidate IC */ l.addi r6,r0,0 l.sll r5,r14,r28 -// l.mul r5,r14,r16 -// l.trap 1 -// l.addi r5,r0,IC_SIZE 1: l.mtspr r0,r6,SPR_ICBIR l.sfne r6,r5 l.bf 1b l.add r6,r6,r14 - // l.addi r6,r6,IC_LINE /* Enable IC */ l.mfspr r6,r0,SPR_SR @@ -918,13 +911,10 @@ _dc_enable: l.sll r14,r30,r28 /* Establish number of cache sets - r16 contains number of cache sets r28 contains log(# of cache sets) */ l.andi r26,r24,SPR_DCCFGR_NCS l.srli r28,r26,3 - l.ori r30,r0,1 - l.sll r16,r30,r28 /* Invalidate DC */ l.addi r6,r0,0 diff --git a/arch/openrisc/kernel/jump_label.c b/arch/openrisc/kernel/jump_label.c index ab7137c23b46c..9cb63f2d2e2b7 100644 --- a/arch/openrisc/kernel/jump_label.c +++ b/arch/openrisc/kernel/jump_label.c @@ -47,5 +47,5 @@ bool arch_jump_label_transform_queue(struct jump_entry *entry, void arch_jump_label_transform_apply(void) { - kick_all_cpus_sync(); + icache_all_inv(); } diff --git a/arch/openrisc/kernel/patching.c b/arch/openrisc/kernel/patching.c index d186172beb337..5db027b78bc40 100644 --- a/arch/openrisc/kernel/patching.c +++ b/arch/openrisc/kernel/patching.c @@ -49,6 +49,9 @@ static int __patch_insn_write(void *addr, u32 insn) waddr = patch_map(addr, FIX_TEXT_POKE0); ret = copy_to_kernel_nofault(waddr, &insn, OPENRISC_INSN_SIZE); + if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH)) + local_dcache_range_flush((unsigned long)waddr, + (unsigned long)waddr + OPENRISC_INSN_SIZE); local_icache_range_inv((unsigned long)waddr, (unsigned long)waddr + OPENRISC_INSN_SIZE); diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c index 040ca201b6927..65599252f3d41 100644 --- a/arch/openrisc/kernel/smp.c +++ b/arch/openrisc/kernel/smp.c @@ -346,3 +346,24 @@ void smp_icache_page_inv(struct page *page) on_each_cpu(ipi_icache_page_inv, page, 1); } EXPORT_SYMBOL(smp_icache_page_inv); + +static void ipi_icache_all_inv(void *arg) +{ + local_icache_all_inv(); +} + +void smp_icache_all_inv(void) +{ + if (num_online_cpus() < 2) { + local_icache_all_inv(); + return; + } + + /* + * Ensure stores complete before we request remote icaches + * to invalidate. + */ + mb(); + + on_each_cpu(ipi_icache_all_inv, NULL, 1); +} diff --git a/arch/openrisc/mm/cache.c b/arch/openrisc/mm/cache.c index f33df46dae4e5..2667d90691b59 100644 --- a/arch/openrisc/mm/cache.c +++ b/arch/openrisc/mm/cache.c @@ -63,6 +63,22 @@ void local_icache_page_inv(struct page *page) } EXPORT_SYMBOL(local_icache_page_inv); +void local_icache_all_inv(void) +{ + if (cpu_cache_is_present(SPR_UPR_ICP)) { + unsigned long iccfgr = mfspr(SPR_ICCFGR); + unsigned long sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); + unsigned long block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); + unsigned long paddr = 0; + unsigned long end = sets * block_size; + + while (paddr < end) { + mtspr(SPR_ICBIR, paddr); + paddr += block_size; + } + } +} + void local_dcache_range_flush(unsigned long start, unsigned long end) { cache_loop(start, end, SPR_DCBFR, SPR_UPR_DCP); diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c index 89d8c6df88551..db7c844faeeb6 100644 --- a/arch/openrisc/mm/init.c +++ b/arch/openrisc/mm/init.c @@ -193,7 +193,7 @@ void __init mem_init(void) return; } -static int __init map_page(unsigned long va, phys_addr_t pa, pgprot_t prot) +static int map_page(unsigned long va, phys_addr_t pa, pgprot_t prot) { p4d_t *p4d; pud_t *pud; |