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| author | Han Gao <gaohan@iscas.ac.cn> | 2026-04-01 01:12:48 +0800 |
|---|---|---|
| committer | Inochi Amaoto <inochiama@gmail.com> | 2026-05-28 09:48:22 +0800 |
| commit | e728a57834d06b9bbf9bbed69e3ea16416d257d5 (patch) | |
| tree | a03feda7511c4beeaf33b1e34d0541d5c77b9d12 /arch | |
| parent | 254f49634ee16a731174d2ae34bc50bd5f45e731 (diff) | |
| download | linux-next-history-e728a57834d06b9bbf9bbed69e3ea16416d257d5.tar.gz | |
riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers
SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all
four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent
so the kernel uses coherent DMA mappings instead of non-coherent bounce
buffering.
Cc: stable@vger.kernel.org
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Link: https://patch.msgid.link/20260331171248.973014-3-gaohan@iscas.ac.cn
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 9fddf3f0b3b99..3af7705497426 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -417,6 +417,7 @@ vendor-id = <0x1f1c>; device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; + dma-coherent; msi-parent = <&msi>; status = "disabled"; }; @@ -439,6 +440,7 @@ vendor-id = <0x1f1c>; device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; + dma-coherent; msi-parent = <&msi>; status = "disabled"; }; @@ -461,6 +463,7 @@ vendor-id = <0x1f1c>; device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; + dma-coherent; msi-parent = <&msi>; status = "disabled"; }; @@ -483,6 +486,7 @@ vendor-id = <0x1f1c>; device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; + dma-coherent; msi-parent = <&msi>; status = "disabled"; }; |