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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2026-05-26 21:40:44 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-28 15:59:05 +0200 |
| commit | f5ef456c2df2276599ab207f1fe82122626c35c4 (patch) | |
| tree | 4dcc5edccfcb2dd4278afb0d04a8abcab824d0f7 /arch | |
| parent | d6bee881ca5128d5e85e1388006dc8abd241ef84 (diff) | |
| download | linux-next-history-f5ef456c2df2276599ab207f1fe82122626c35c4.tar.gz | |
arm64: dts: renesas: r9a09g087: Add xSPI nodes
Add device tree nodes for the two xSPI (Expanded SPI) controllers
integrated into the RZ/N2H (R9A09G087) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260526204045.3481604-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index c64b532f3d234..e8d4f76949ccb 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -1009,6 +1009,46 @@ }; }; + xspi0: spi@801c0000 { + compatible = "renesas,r9a09g087-xspi", + "renesas,r9a09g047-xspi"; + reg = <0 0x801c0000 0 0x1000>, + <0 0x40000000 0 0x10000000>; + reg-names = "regs", "dirmap"; + interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pulse", "err_pulse"; + clocks = <&cpg CPG_MOD 4>, + <&cpg CPG_CORE R9A09G087_XSPI_CLK0>; + clock-names = "ahb", "spi"; + resets = <&cpg 4>; + reset-names = "hresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + xspi1: spi@801c1000 { + compatible = "renesas,r9a09g087-xspi", + "renesas,r9a09g047-xspi"; + reg = <0 0x801c1000 0 0x1000>, + <0 0x50000000 0 0x10000000>; + reg-names = "regs", "dirmap"; + interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pulse", "err_pulse"; + clocks = <&cpg CPG_MOD 5>, + <&cpg CPG_CORE R9A09G087_XSPI_CLK1>; + clock-names = "ahb", "spi"; + resets = <&cpg 5>; + reset-names = "hresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@80280000 { compatible = "renesas,r9a09g087-cpg-mssr"; reg = <0 0x80280000 0 0x10000>, |