tristate "AdvanSys SCSI support"

depends on SCSI

depends on (ISA || EISA || PCI) && HAS_IOPORT

help

This is a driver for all SCSI host adapters manufactured by

AdvanSys. It is documented in the kernel source in

sr_mod-objs := sr.o sr_ioctl.o sr_vendor.o

ncr53c8xx-flags-$(CONFIG_SCSI_ZALON) \

CFLAGS_ncr53c8xx.o := $(ncr53c8xx-flags-y) $(ncr53c8xx-flags-m)

zalon7xx-objs := zalon.o ncr53c8xx.o

#include <linux/dmapool.h>

#include <asm/io.h>

#include <scsi/scsi_cmnd.h>

#include <scsi/scsi_device.h>

return 0;

if (!device_link_add(&sdev->sdev_gendev, dev,

if (pm_runtime_enabled(dev)) {

dev_info(dev, "add device link failed, disable runtime PM for the host\n");

pm_runtime_disable(dev);

return 0;

}

static struct attribute *host_v3_hw_attrs[] = {

&dev_attr_phy_event_threshold.attr,

&dev_attr_intr_conv_v3_hw.attr,

.sg_tablesize = HISI_SAS_SGE_PAGE_CNT,

.sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT,

.sdev_init = hisi_sas_sdev_init,

.shost_groups = host_v3_hw_groups,

.sdev_groups = sdev_groups_v3_hw,

.tag_alloc_policy_rr = true,

#define SCU_CONTEXT_COMMAND_LOGICAL_PORT_SHIFT 12

#define SCU_CONTEXT_COMMAND_LOGICAL_PORT_MASK 0x00007000

#define MAKE_SCU_CONTEXT_COMMAND_TYPE(type) \

* This can be used by software iscsi_transports that allocate

* a session per scsi host.

*

* tasks they support. The iscsi layer reserves ISCSI_MGMT_CMDS_MAX tasks

* for nop handling and login/logout requests.

*/

if (conn->ping_timeout && !conn->recv_timeout) {

iscsi_conn_printk(KERN_ERR, conn, "invalid recv timeout of "

conn->recv_timeout = 5;

}

#define MVS_ID_NOT_MAPPED 0x7f

#define WIDE_PORT_MAX_PHY 4

#define mv_printk(fmt, arg ...) \

#ifdef MV_DEBUG

#else

#define mv_dprintk(format, arg...) no_printk(format, ## arg)

#endif

** return from the subroutine.

*/

#define PREFETCH_FLUSH_CNT 2

#define PREFETCH_FLUSH SCR_CALL, PADDRH (wait_dma),

#else

#else

/* Only 8 or 32 bit transfers allowed */

#define INW_OFF(o) (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1))

#else

#endif

#define INL_OFF(o) readl_raw((char __iomem *)np->reg + (o))

/* Only 8 or 32 bit transfers allowed */

#define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)

#else

goto out;

}

for (i = 0; flash_command_table[i].code != FLASH_CMD_NONE; i++) {

if (!memcmp(flash_command_table[i].command,

cmd_ptr, strlen(cmd_ptr))) {

char *buf_copy = buf;

temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;

if (++pm8001_ha->non_fatal_count == 1) {

if (pm8001_ha->chip_id == chip_8001) {

snprintf(pm8001_ha->forensic_info.data_buf.direct_data,

}

/**

* @sdev: holds information to be stored in the new scsi_device

* @inq_result: holds the result of a previous INQUIRY to the LUN

* @bflags: black/white list flag

if (rport->reconnect_delay <= 0 && delay > 0 &&

rport->state != SRP_RPORT_RUNNING) {

delay * HZ);

} else if (delay <= 0) {

cancel_delayed_work(&rport->reconnect_work);

delay = rport->reconnect_delay *

clamp(rport->failed_reconnects - 10, 1, 100);

if (delay > 0)

&rport->reconnect_work, delay * HZ);

}

}

if (rport->state == SRP_RPORT_LOST)

return;

if (delay > 0)

1UL * delay * HZ);

if ((fast_io_fail_tmo >= 0 || dev_loss_tmo >= 0) &&

srp_rport_set_state(rport, SRP_RPORT_BLOCKED) == 0) {

rport->state);

scsi_block_targets(shost, &shost->shost_gendev);

if (fast_io_fail_tmo >= 0)

&rport->fast_io_fail_work,

1UL * fast_io_fail_tmo * HZ);

if (dev_loss_tmo >= 0)

&rport->dev_loss_work,

1UL * dev_loss_tmo * HZ);

}

case RES_TYPE_INTR_PBA_LEGACY:

case RES_TYPE_DEVCMD:

case RES_TYPE_DEVCMD2:

break;

default:

#define STORVSC_LOGGING_WARN 2

static int logging_level = STORVSC_LOGGING_ERROR;

MODULE_PARM_DESC(logging_level,

"Logging level, 0 - None, 1 - Error (default), 2 - Warning.");

static int storvsc_vcpus_per_sub_channel = 4;

static unsigned int storvsc_max_hw_queues;

MODULE_PARM_DESC(storvsc_ringbuffer_size, "Ring buffer size (bytes)");

module_param(storvsc_max_hw_queues, uint, 0644);

MODULE_PARM_DESC(storvsc_max_hw_queues, "Maximum number of hardware queues");

MODULE_PARM_DESC(storvsc_vcpus_per_sub_channel, "Ratio of VCPUs to subchannels");

static int ring_avail_percent_lowater = 10;

MODULE_PARM_DESC(ring_avail_percent_lowater,

"Select a channel if available ring size > this in percent");

u64 exception_id;

int err;

ufshcd_rpm_get_sync(hba);

ufshcd_rpm_put_sync(hba);

if (err)

idn <= QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE;

}

static int wb_read_resize_attrs(struct ufs_hba *hba,

enum attr_idn idn, u32 *attr_val)

{

struct device_attribute *attr, char *buf) \

{ \

struct ufs_hba *hba = dev_get_drvdata(dev); \

u32 value; \

int ret; \

u8 index = 0; \

if (ufshcd_is_wb_attrs(QUERY_ATTR_IDN##_uname)) \

index = ufshcd_wb_get_query_index(hba); \

ufshcd_rpm_get_sync(hba); \

ufshcd_rpm_put_sync(hba); \

if (ret) { \

ret = -EINVAL; \

goto out; \

} \

out: \

up(&hba->host_sem); \

return ret; \

#include <ufs/unipro.h>

#include "ufshcd-priv.h"

static bool use_adaptive_txeq;

module_param(use_adaptive_txeq, bool, 0644);

MODULE_PARM_DESC(use_adaptive_txeq, "Find and apply optimal TX Equalization settings before changing Power Mode (default: false)");

module_param_array(txeq_presets_selected, bool, NULL, 0644);

MODULE_PARM_DESC(txeq_presets_selected, "Use only the selected Presets out of the 8 TX Equalization Presets for TX EQTR");

/*

* ufs_tx_eq_preset - Table of minimum required list of presets.

*

PA_TXEQG6SETTING

};

/**

* ufshcd_configure_precoding - Configure Pre-Coding for all active lanes

* @hba: per adapter instance

/* Mark TX Equalization settings as valid */

params->is_valid = true;

params->is_applied = false;

}

return ret;

}

u32 *attr_val);

int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,

enum attr_idn idn, u8 index, u8 selector, u32 *attr_val);

int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,

enum flag_idn idn, u8 index, bool *flag_res);

void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);

enum query_opcode desc_op);

int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);

int ufshcd_uic_tx_eqtr(struct ufs_hba *hba, int gear);

void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba);

bool ufshcd_is_txeq_presets_used(struct ufs_hba *hba);

bool ufshcd_is_txeq_preset_selected(u8 preshoot, u8 deemphasis);

int ufshcd_retrain_tx_eq(struct ufs_hba *hba, u32 gear);

/* Wrapper functions for safely calling variant operations */

static inline const char *ufshcd_get_var_name(struct ufs_hba *hba)

return ret;

}

/*

* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;

* < 0 if another error occurred.

}

EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);

/**

* ufshcd_link_startup - Initialize unipro link startup

* @hba: per adapter instance

goto out;

}

/* Include any host controller configuration via UIC commands */

ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);

if (ret)

__func__, err);

}

static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)

{

u8 index;

dev_err(hba->dev,

"%s: Failed getting max supported power mode\n",

__func__);

out:

return ret;

}

static void ufshcd_set_timestamp_attr(struct ufs_hba *hba)

{

struct ufs_dev_info *dev_info = &hba->dev_info;

if (dev_info->wspecversion < 0x400 ||

hba->dev_quirks & UFS_DEVICE_QUIRK_NO_TIMESTAMP_SUPPORT)

return;

if (err)

dev_err(hba->dev, "%s: failed to set timestamp %d\n",

__func__, err);

}

/**

/* Turn on everything while shutting down */

ufshcd_rpm_get_sync(hba);

scsi_device_quiesce(sdev);

shost_for_each_device(sdev, hba->host) {

if (sdev == hba->ufs_device_wlun)

If unsure, say N.

config SCSI_UFS_QCOM

depends on SCSI_UFSHCD_PLATFORM && ARCH_QCOM

depends on GENERIC_MSI_IRQ

depends on RESET_CONTROLLER

};

static const struct pci_device_id tc_dwc_g210_pci_tbl[] = {

{ } /* terminate list */

};

#define UFS_EXYNOSAUTO_RD_SHARABLE BIT(1)

#define UFS_EXYNOSAUTO_SHARABLE (UFS_EXYNOSAUTO_WR_SHARABLE | \

UFS_EXYNOSAUTO_RD_SHARABLE)

#define UFS_GS101_WR_SHARABLE BIT(1)

#define UFS_GS101_RD_SHARABLE BIT(0)

#define UFS_GS101_SHARABLE (UFS_GS101_WR_SHARABLE | \

return 0;

}

/*

* exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w

* Control should be disabled in the below cases

.suspend = gs101_ufs_suspend,

};

static const struct of_device_id exynos_ufs_of_match[] = {

{ .compatible = "google,gs101-ufs",

.data = &gs101_ufs_drvs },

.data = &exynosauto_ufs_drvs },

{ .compatible = "samsung,exynosautov9-ufs-vh",

.data = &exynosauto_ufs_vh_drvs },

{ .compatible = "tesla,fsd-ufs",

.data = &fsd_ufs_drvs },

{},

return 0;

}

static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,

enum ufs_notify_change_status status)

{

err = ufshcd_disable_host_tx_lcc(hba);

break;

default:

break;

}

*/

#define NUM_TX_R1W1 13

static inline void

ufs_qcom_get_controller_revision(struct ufs_hba *hba,

u8 *major, u16 *minor, u16 *step)

};

static const struct pci_device_id ufshcd_pci_tbl[] = {

{ } /* terminate list */

};