+\fB--cpu cpu-set\fP limit output to system summary plus the specified cpu-set. If cpu-set is the string "core", then the system summary plus the first CPU in each core are printed -- eg. subsequent HT siblings are not printed. Or if cpu-set is the string "package", then the system summary plus the first CPU in each package is printed. Otherwise, the system summary plus the specified set of CPUs are printed. The cpu-set is ordered from low to high, comma delimited with ".." and "-" permitted to denote a range. eg. 1,2,8,14..17,21-44 Multiple invocations of --cpu are OR'd together.

+ Core CPU Avg_MHz Busy% Bzy_MHz TSC_MHz CPU%c7 UncMHz

+ Core CPU Avg_MHz Busy% Bzy_MHz TSC_MHz CPU%c7 UncMHz

+FILE *outf;

+

+#define bic_set_t cpu_set_t /* implement bic_set_t using cpu_set_t */

+

+/*

+ * debug helper

+ */

+static void print_bic_set(const char *s, const bic_set_t *set)

+ fprintf(outf, "%s:", s);

+ fprintf(outf, " %s", bic[i].name);

+ fputc('\n', outf);

+static bic_set_t bic_group_topology;

+static bic_set_t bic_group_thermal_pwr;

+static bic_set_t bic_group_frequency;

+static bic_set_t bic_group_hw_idle;

+static bic_set_t bic_group_sw_idle;

+static bic_set_t bic_group_idle;

+static bic_set_t bic_group_cache;

+static bic_set_t bic_group_other;

+static bic_set_t bic_group_disabled_by_default;

+static bic_set_t bic_enabled;

+static bic_set_t bic_present;

+

+static void dump_bic_sets(void)

+{

+ print_bic_set("bic_enabled", &bic_enabled);

+ print_bic_set("bic_present", &bic_present);

+ print_bic_set("bic_group_topology", &bic_group_topology);

+ print_bic_set("bic_group_thermal_pwr", &bic_group_thermal_pwr);

+ print_bic_set("bic_group_frequency", &bic_group_frequency);

+ print_bic_set("bic_group_hw_idle", &bic_group_hw_idle);

+ print_bic_set("bic_group_sw_idle", &bic_group_sw_idle);

+ print_bic_set("bic_group_idle", &bic_group_idle);

+ print_bic_set("bic_group_cache", &bic_group_cache);

+ print_bic_set("bic_group_other", &bic_group_other);

+ print_bic_set("bic_group_disabled_by_default", &bic_group_disabled_by_default);

+}

+static void bic_set_all(bic_set_t *set)

+static void bic_clear_bits(bic_set_t *dst, bic_set_t *clr)

+bool force_load;

+void get_msr(int cpu, off_t offset, unsigned long long *msr);

+int add_counter(unsigned int, const char *, const char *, unsigned int, enum counter_scope, enum counter_type, enum counter_format, int, int);

+ get_msr(master_cpu, MSR_FSB_FREQ, &msr);

+ fprintf(outf, "SLM BCLK: unknown\n");

+ fprintf(outf, "SLM BCLK: %.1f MHz\n", freq);

+ force_load = true;

+ if ((force_load == true) && !platform) {

+cpu_set_t *cpu_present_set, *cpu_possible_set, *cpu_effective_set, *cpu_allowed_set, *cpu_affinity_set, *cpuset_cmdline;

+size_t cpu_setsize;

+ return (sscanf(e->d_name, "telem%u", &dummy) == 1);

+ if (sscanf((*a)->d_name, "telem%u", &aidx) != 1)

+ aidx = 0;

+ if (sscanf((*b)->d_name, "telem%u", &bidx) != 1)

+ bidx = 0;

+ if (num_names == -1) {

+ closedir(iter->dir);

+ iter->dir = NULL;

+ }

+ if (iter->dir) {

+ closedir(iter->dir);

+ iter->dir = NULL;

+ }

+ return !CPU_ISSET_S(cpu, cpu_setsize, cpu_present_set);

+ return !CPU_ISSET_S(cpu, cpu_setsize, cpu_allowed_set);

+ CPU_ZERO_S(cpu_setsize, cpu_affinity_set);

+ CPU_SET_S(cpu, cpu_setsize, cpu_affinity_set);

+ if (sched_setaffinity(0, cpu_setsize, cpu_affinity_set) == -1)

+void get_msr(int cpu, off_t offset, unsigned long long *msr)

+ if (pread(get_msr_fd(cpu), msr, sizeof(*msr), offset) != sizeof *msr)

+void bic_lookup(bic_set_t *ret_set, char *name_list, enum show_hide_mode mode)

+ if ((t != average.threads) && (cpuset_cmdline && !CPU_ISSET_S(t->cpu_id, cpu_setsize, cpuset_cmdline)))

+ get_msr(cpu, mp->msr_num, counterp);

+ if (rci->flags[i] & RAPL_COUNTER_FLAG_USE_MSR_SUM)

+ get_msr_sum(cpu, rci->msr[i], &rci->data[i]);

+ else

+ get_msr(cpu, rci->msr[i], &rci->data[i]);

+ get_msr(cpu, cci->msr[i], &cci->data[i]);

+ get_msr(cpu, mci->msr[i], &mci->data[i]);

+ get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us);

+ get_msr(cpu, MSR_IA32_THERM_STATUS, &msr);

+ if (DO_BIC(BIC_Totl_c0))

+ get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0);

+ if (DO_BIC(BIC_Any_c0))

+ get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0);

+ if (DO_BIC(BIC_GFX_c0))

+ get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0);

+ if (DO_BIC(BIC_CPUGFX))

+ get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0);

+ get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr);

+ for (i = 0; i <= topo.max_cpu_num; ++i) {

+ for (int i = 0; i <= topo.max_cpu_num; ++i) {

+ for (int i = 0; i <= topo.max_cpu_num; ++i) {

+ for (int i = 0; i <= topo.max_cpu_num; ++i) {

+ for (int cpu = 0; cpu <= topo.max_cpu_num; ++cpu) {

+ int start, end;

+ if (start > topo.max_cpu_num)

+ if (start > topo.max_cpu_num)

+ if (parse_cpu_str(cpu_effective_str, cpu_effective_set, cpu_setsize))

+ CPU_SET_S(cpu, cpu_setsize, cpu_present_set);

+ int idx;

+ get_msr(cpu, offset, &msr_cur);

+ int i;

+ get_msr(cpu, offset, &msr_cur);

+ get_msr(cpu, MSR_PM_ENABLE, &msr);

+ get_msr(cpu, MSR_HWP_CAPABILITIES, &msr);

+ get_msr(cpu, MSR_HWP_REQUEST, &msr);

+ get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr);

+ get_msr(cpu, MSR_HWP_INTERRUPT, &msr);

+ get_msr(cpu, MSR_HWP_STATUS, &msr);

+ if (valid_rapl_msrs & RAPL_PKG_POWER_INFO) {

+ get_msr(master_cpu, MSR_PKG_POWER_INFO, &msr);

+ return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;

+ }

+ get_msr(master_cpu, MSR_RAPL_POWER_UNIT, &msr);

+ get_msr(master_cpu, MSR_RAPL_PWR_UNIT, &msr);

+ warn("%s", path);

+ get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr);

+ get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr);

+ get_msr(cpu, MSR_PKG_POWER_INFO, &msr);

+ get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr);

+ get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr);

+ get_msr(cpu, MSR_DRAM_POWER_INFO, &msr);

+ get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr);

+ get_msr(cpu, MSR_PP0_POLICY, &msr);

+ get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr);

+ get_msr(cpu, MSR_PP1_POLICY, &msr);

+ get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr);

+ get_msr(master_cpu, offset, &msr_value);

+ get_msr(master_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr);

+ if (bits) {

+ get_msr(master_cpu, MSR_PLATFORM_INFO, &enabled);

+ }

+ get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr);

+ get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr);

+ get_msr(cpu, MSR_IA32_THERM_STATUS, &msr);

+ get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr);

+ get_msr(master_cpu, MSR_IA32_FEAT_CTL, &msr);

+ fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",

+ master_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : "");

+ get_msr(master_cpu, MSR_IA32_MISC_ENABLE, &msr);

+ fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",

+ master_cpu, msr,

+ msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",

+ msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",

+ msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-",

+ msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");

+ get_msr(master_cpu, MSR_MISC_FEATURE_CONTROL, &msr);

+ fprintf(outf,

+ "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",

+ master_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "", msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : "");

+ get_msr(master_cpu, MSR_MISC_PWR_MGMT, &msr);

+ fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",

+ master_cpu, msr, msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS");

+ get_msr(master_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr);

+ fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", master_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");

+ get_msr(master_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr);

+ fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", master_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");

+ if (parse_cpu_str(cpuset_buf, cpu_set, cpu_setsize)) {

+ CPU_ZERO_S(cpu_setsize, perf_pcore_set);

+ CPU_ZERO_S(cpu_setsize, perf_ecore_set);

+ CPU_ZERO_S(cpu_setsize, perf_lcore_set);

+ for (int cpu = 0; cpu <= topo.max_cpu_num; ++cpu) {

+ get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch);

+ ucode_patch_valid = true;

+ if (!authentic_amd && !hygon_genuine)

+ ucode_patch >>= 32;

+ if (perf_pcore_set && CPU_ISSET_S(cpu, cpu_setsize, perf_pcore_set)) {

+ } else if (perf_ecore_set && CPU_ISSET_S(cpu, cpu_setsize, perf_ecore_set)) {

+ } else if (perf_lcore_set && CPU_ISSET_S(cpu, cpu_setsize, perf_lcore_set)) {

+/*

+ * get_max_cpu_num(path)

+ * return the last number of the cpu list in this file

+ */

+static int get_max_cpu_num(char *path)

+{

+ FILE *filep;

+ int retval, num;

+ char c;

+

+ filep = fopen(path, "r");

+ if (filep == NULL) {

+ warn("%s", path);

+ return 255;

+ }

+

+ while ((retval = fscanf(filep, "%d%c", &num, &c)) == 2) {

+ if (c == '\n')

+ break;

+ if (c != ',' && c != '-')

+ errx(1, "Bad Format '%s'", path);

+ }

+ if (retval != 2)

+ errx(1, "Bad format '%s'", path);

+

+ fclose(filep);

+ return num;

+}

+

+ /* Initialize num_cpus */

+ CPU_ZERO_S(cpu_setsize, cpu_present_set);

+ CPU_ZERO_S(cpu_setsize, cpu_possible_set);

+ CPU_ZERO_S(cpu_setsize, cpu_effective_set);

+ CPU_ZERO_S(cpu_setsize, cpu_allowed_set);

+ * Make sure all cpus in cpuset_cmdline are also in cpu_present_set during startup.

+ * Give a warning when cpus in cpuset_cmdline become unavailable at runtime.

+ * cpu_allowed_set is the intersection of cpu_present_set/cpu_effective_set/cpuset_cmdline.

+ for (i = 0; i <= topo.max_cpu_num; ++i) {

+ if (cpuset_cmdline && !CPU_ISSET_S(i, cpu_setsize, cpuset_cmdline))

+ if (!CPU_ISSET_S(i, cpu_setsize, cpu_present_set)) {

+ if (cpuset_cmdline) {

+ /* cpus in cpuset_cmdline must be in cpu_present_set during startup */

+ errx(1, "cpu%d not present", i);

+ if (CPU_COUNT_S(cpu_setsize, cpu_effective_set)) {

+ if (!CPU_ISSET_S(i, cpu_setsize, cpu_effective_set)) {

+ CPU_SET_S(i, cpu_setsize, cpu_allowed_set);

+ if (!CPU_COUNT_S(cpu_setsize, cpu_allowed_set))

+ errx(-ENODEV, "No valid cpus found");

+ sched_setaffinity(0, cpu_setsize, cpu_allowed_set);

+ CPU_ZERO_S(cpu_setsize, cpu_affinity_set);

+ for (i = 0; i <= topo.max_cpu_num; i++)

+ for (i = 0; i <= topo.max_cpu_num; ++i) {

+ for (int cpu = 0; cpu <= topo.max_cpu_num; ++cpu) {

+ for (cpu_num = 0; cpu_num <= topo.max_cpu_num;) {

+ if (sched_setaffinity(0, cpu_setsize, cpu_possible_set)) {

+ if (sched_setaffinity(0, cpu_setsize, cpu_allowed_set))

+struct msr_counter *find_msrp_by_name(struct msr_counter *head, const char *name)

+int add_counter(unsigned int msr_num, const char *path, const char *name,

+ if (sys.added_thread_counters >= MAX_ADDED_THREAD_COUNTERS) {

+ sys.added_thread_counters++;

+ if (sys.added_core_counters >= MAX_ADDED_CORE_COUNTERS) {

+ sys.added_core_counters++;

+ if (sys.added_package_counters >= MAX_ADDED_PACKAGE_COUNTERS) {

+ sys.added_package_counters++;

+ if (sp == NULL)

+ err(-1, "%s", path);

+ * 1,2,4..6,8-10 and set bits in cpuset_cmdline

+ if (cpuset_cmdline)

+ if (cpuset_cmdline)

+ /*

+ * cpuset_cmdline is allocated on the first invocation of --cpu

+ * It is re-used for subsequent invocations.

+ * It is never freed.

+ */

+ if (!cpuset_cmdline) {

+ cpuset_cmdline = CPU_ALLOC(topo.max_cpu_num + 1);

+ if (cpuset_cmdline == NULL)

+ err(3, "CPU_ALLOC");

+ CPU_ZERO_S(cpu_setsize, cpuset_cmdline);

+ }

+ if (parse_cpu_str(optarg, cpuset_cmdline, cpu_setsize))

+ if (debug)

+ print_cpu_set("--cpu", cpuset_cmdline);

+ force_load = true;

+ bic_set_t bic_group_hide;

+ warn("/sys/fs/cgroup/cgroup.procs");

+

+ /* probe max_cpu_num and set cpu_setsize early for use by cmdline() */

+ topo.max_cpu_num = get_max_cpu_num("/sys/devices/system/cpu/possible");

+ cpu_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));

+

+ if (dump_only) {

+ dump_bic_sets();

+ }