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path: root/drivers/cxl/cxl.h
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2026-04-10Merge branch 'for-7.1/cxl-misc' into cxl-for-nextDave Jiang1-1/+10
2026-04-10cxl/hdm: Add support for 32 switch decodersLi Ming1-1/+10
2026-04-03Merge branch 'for-7.1/cxl-region-refactor' into cxl-for-nextDave Jiang1-0/+1
2026-04-03Merge branch 'for-7.1/dax-hmem' into cxl-for-nextDave Jiang1-2/+9
2026-04-03Merge branch 'for-7.1/cxl-type2-support' into cxl-for-nextDave Jiang1-98/+1
2026-04-01cxl/region: Constify cxl_region_resource_contains()Dan Williams1-2/+2
2026-04-01cxl/region: Limit visibility of cxl_region_contains_resource()Dan Williams1-0/+5
2026-04-01cxl/region: Fix use-after-free from auto assembly failureDan Williams1-2/+4
2026-03-27cxl/core: use cleanup.h for devm_cxl_add_dax_regionGregory Price1-0/+1
2026-03-20cxl: Add endpoint decoder flags clear when PCI reset happensDave Jiang1-0/+1
2026-03-16cxl: Move pci generic code from cxl_pci to core/cxl_pciAlejandro Lucero1-2/+0
2026-03-16cxl: export internal structs for external Type2 driversAlejandro Lucero1-96/+1
2026-02-24cxl: Fix race of nvdimm_bus object when creating nvdimm objectsDave Jiang1-0/+5
2026-02-23cxl: Move devm_cxl_add_nvdimm_bridge() to cxl_pmem.koDave Jiang1-0/+2
2026-02-04Merge branch 'for-7.0/cxl-prm-translation' into cxl-for-nextDave Jiang1-10/+30
2026-02-04cxl: Disable HPA/SPA translation handlers for Normalized AddressingRobert Richter1-1/+8
2026-02-04cxl: Enable AMD Zen5 address translation using ACPI PRMTRobert Richter1-0/+7
2026-02-03cxl: Introduce callback for HPA address ranges translationRobert Richter1-0/+1
2026-02-03cxl: Simplify cxl_root_ops allocation and handlingRobert Richter1-9/+10
2026-02-03cxl/region: Store HPA range in struct cxl_regionRobert Richter1-0/+2
2026-02-03cxl/region: Store root decoder in struct cxl_regionRobert Richter1-0/+2
2026-02-02Merge branch 'for-7.0/cxl-aer-prep' into cxl-for-nextDave Jiang1-19/+14
2026-02-02cxl/port: Map Port RAS registersTerry Bowman1-0/+2
2026-02-02cxl/port: Move dport probe operations to a driver eventDan Williams1-19/+12
2026-01-23Merge branch 'for-7.0/cxl-init' into cxl-for-nextDave Jiang1-0/+2
2026-01-22cxl/mem: Clarify @host for devm_cxl_add_nvdimm()Dan Williams1-1/+2
2026-01-22cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from...Dave Jiang1-8/+0
2026-01-05cxl/port: Arrange for always synchronous endpoint attachDan Williams1-0/+2
2025-11-14Merge branch 'for-6.19/cxl-prm' into cxl-for-nextDave Jiang1-1/+1
2025-11-14cxl: Simplify cxl_rd_ops allocation and handlingRobert Richter1-1/+1
2025-11-13Merge branch 'for-6.19/cxl-addr-xlat' into cxl-for-nextDave Jiang1-0/+19
2025-11-12cxl: Add handling of locked CXL decoderDave Jiang1-0/+8
2025-11-03cxl/acpi: Make the XOR calculations available for testingAlison Schofield1-0/+13
2025-11-03cxl/region: Refactor address translation funcs for testingAlison Schofield1-0/+6
2025-09-18Merge branch 'for-6.18/cxl-delay-dport' into cxl-for-nextDave Jiang1-9/+34
2025-09-18cxl: Move port register setup to when first dport appearDave Jiang1-0/+2
2025-09-18cxl: Change sslbis handler to only handle single dportDave Jiang1-1/+1
2025-09-18cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup()Dave Jiang1-0/+2
2025-09-18cxl/test: Add mock version of devm_cxl_add_dport_by_dev()Dave Jiang1-0/+20
2025-09-18cxl/test: Refactor decoder setup to reduce cxl_test burdenDave Jiang1-6/+3
2025-09-17cxl: Add a cached copy of target_map to cxl_decoderDave Jiang1-2/+6
2025-08-12cxl: Define a SPA->CXL HPA root decoder callback for XOR MathAlison Schofield1-0/+2
2025-08-12cxl: Move hpa_to_spa callback to a new root decoder ops structureAlison Schofield1-3/+9
2025-08-01Merge tag 'cxl-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds1-13/+4
2025-07-31Merge tag 'mm-stable-2025-07-30-15-25' of git://git.kernel.org/pub/scm/linux/...Linus Torvalds1-2/+2
2025-07-16Merge branch 'for-6.17/cxl-acquire' into cxl-for-nextDave Jiang1-12/+1
2025-07-16cxl: Convert to ACQUIRE() for conditional rwsem lockingDan Williams1-12/+1
2025-07-15cxl: Remove core/acpi.c and cxl core dependency on ACPIRobert Richter1-0/+2
2025-07-13drivers,cxl: use node-notifier instead of memory-notifierOscar Salvador1-2/+2
2025-07-01cxl: Include range.h in cxl.hNathan Chancellor1-0/+1
2025-07-01cxl: make cxl_bus_type constantGreg Kroah-Hartman1-1/+1
2025-05-23Merge branch 'for-6.16/cxl-features-ras' into cxl-for-nextDave Jiang1-0/+10
2025-05-23cxl/edac: Add CXL memory device patrol scrub control featureShiju Jose1-0/+10
2025-05-09cxl/region: Factor out code to find a root decoder's regionRobert Richter1-0/+1
2025-05-09cxl/region: Factor out code to find the root decoderRobert Richter1-0/+1
2025-05-09cxl/port: Replace put_cxl_root() by a cleanup helperRobert Richter1-2/+2
2025-05-09cxl/region: Move find_cxl_root() to cxl_add_to_region()Robert Richter1-4/+2
2025-05-09cxl: Introduce parent_port_of() helperRobert Richter1-0/+1
2025-04-09cxl/pci: Drop the parameter is_port of cxl_gpf_get_dvsec()Li Ming1-1/+1
2025-04-09cxl/core: Fix caching dport GPF DVSEC issueLi Ming1-2/+2
2025-03-14Merge branch 'for-6.15/extended-linear-cache' into cxl-for-next2Dave Jiang1-0/+8
2025-03-14Merge branch 'for-6.15/dirty-shutdown' into cxl-for-next2Dave Jiang1-0/+5
2025-03-14cxl/pmem: Export dirty shutdown count via sysfsDavidlohr Bueso1-0/+1
2025-03-14cxl/pci: Introduce cxl_gpf_get_dvsec()Davidlohr Bueso1-0/+2
2025-03-14cxl/pci: Support Global Persistent Flush (GPF)Davidlohr Bueso1-0/+2
2025-02-26cxl: Add mce notifier to emit aliased address for extended linear cacheDave Jiang1-0/+6
2025-02-26acpi/hmat / cxl: Add extended linear cache support for CXLDave Jiang1-0/+2
2025-02-04cxl: Kill enum cxl_decoder_modeDan Williams1-28/+9
2025-02-04cxl: Remove the CXL_DECODER_MIXED mistakeDan Williams1-3/+1
2025-01-29Merge tag 'cxl-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds1-2/+4
2025-01-22cxl/core/regs: Refactor out functions to count regblocks of given typeHuaisheng Ye1-1/+2
2025-01-03cxl/pmem: Remove is_cxl_nvdimm_bridge()Zijun Hu1-1/+0
2025-01-02cxl/pci: Add CXL Type 1/2 support to cxl_dvsec_rr_decode()Alejandro Lucero1-1/+2
2024-11-22Merge tag 'cxl-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds1-0/+9
2024-10-28cxl/core/regs: Add rcd_pcie_cap initializationKobayashi,Daisuke1-0/+9
2024-10-25cxl/port: Fix use-after-free, permit out-of-order decoder shutdownDan Williams1-1/+2
2024-09-22cxl: Calculate region bandwidth of targets with shared upstream linkDave Jiang1-0/+1
2024-09-09cxl/pci: Remove duplicated implementation of waiting for memory_info_validYanfei Xu1-1/+1
2024-09-03cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()Li Ming1-2/+3
2024-09-03cxl/port: Use __free() to drop put_device() for cxl_portLi Ming1-0/+1
2024-07-28Merge tag 'cxl-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds1-7/+6
2024-07-25Merge tag 'driver-core-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds1-4/+1
2024-07-11Merge branch 'for-6.11/xor_fixes' into cxl-for-nextDave Jiang1-7/+4
2024-07-11cxl: Remove defunct code calculating host bridge target positionsAlison Schofield1-7/+1
2024-07-11cxl: Restore XOR'd position bits during address translationAlison Schofield1-0/+3
2024-07-03driver core: have match() callback in struct bus_type take a const *Greg Kroah-Hartman1-4/+1
2024-07-02cxl/region: Support to calculate memory tier abstract distanceHuang Ying1-0/+2
2024-06-25cxl/region: check interleave capabilityYao Xingtao1-0/+2
2024-06-18cxl/mem: Fix no cxl_nvd during pmem region auto-assemblingLi Ming1-2/+2
2024-05-21Merge tag 'pci-v6.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds1-0/+2
2024-05-08cxl: Add post-reset warning if reset results in loss of previously committed ...Dave Jiang1-0/+2
2024-05-01cxl/acpi: Cleanup __cxl_parse_cfmws()Dan Williams1-0/+5
2024-04-30cxl: Fix compile warning for cxl_security_ops externDave Jiang1-0/+2
2024-04-08cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coordDave Jiang1-4/+2
2024-04-08cxl: Fix incorrect region perf data calculationDave Jiang1-2/+0
2024-03-12cxl/region: Add memory hotplug notifier for cxl regionDave Jiang1-0/+3
2024-03-12cxl/region: Calculate performance data for a regionDave Jiang1-0/+4
2024-03-12cxl: Split out host bridge access coordinatesDave Jiang1-0/+2
2024-03-12cxl: Split out combine_coordinates() for common shared usageDave Jiang1-0/+4
2024-03-12ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access c...Dave Jiang1-1/+1
2024-02-16cxl: Fix sysfs export of qos_class for memdevDave Jiang1-0/+2
2024-01-05Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams1-2/+0
2024-01-05cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang1-7/+7
2024-01-05cxl: Introduce put_cxl_root() helperDave Jiang1-0/+3
2024-01-04cxl/port: Fix missing target list lockDan Williams1-2/+0
2023-12-22cxl: Add helper function that calculate performance data for downstream portsDave Jiang1-0/+3
2023-12-22cxl: Store the access coordinates for the generic portsDave Jiang1-0/+2
2023-12-22cxl: Calculate and store PCI link latency for the downstream portsDave Jiang1-0/+4
2023-12-22cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang1-0/+25
2023-12-22cxl: Add callback to parse the SSLBIS subtable from CDATDave Jiang1-0/+4
2023-12-22cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang1-0/+2
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams1-0/+1
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams1-0/+3
2023-10-27cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang1-0/+3
2023-10-27cxl: Add cxl_decoders_committed() helperDave Jiang1-0/+1
2023-10-27cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter1-2/+1
2023-10-27cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman1-0/+10
2023-10-27cxl/pci: Add RCH downstream port AER register discoveryRobert Richter1-0/+7
2023-10-27cxl/port: Remove Component Register base address from struct cxl_portRobert Richter1-2/+0
2023-10-27cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter1-4/+4
2023-10-27cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter1-2/+2
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-25/+32
2023-06-25Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams1-0/+16
2023-06-25Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams1-7/+9
2023-06-25Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams1-6/+5
2023-06-25Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams1-1/+0
2023-06-25cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams1-1/+1
2023-06-25cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams1-2/+2
2023-06-25cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams1-2/+2
2023-06-25cxl/region: Flag partially torn down regions as unusableDan Williams1-0/+8
2023-06-25cxl/region: Move cache invalidation before region teardown, and before setupDan Williams1-7/+1
2023-06-25cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter1-0/+2
2023-06-25cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter1-0/+2
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter1-0/+2
2023-06-25cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter1-2/+0
2023-06-25cxl/pci: Refactor component register discovery for reuseTerry Bowman1-0/+1
2023-06-25cxl/core/regs: Add @dev to cxl_register_mapRobert Richter1-4/+6
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-6/+7
2023-06-25cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter1-2/+2
2023-06-25cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams1-2/+7
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter1-9/+3
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron1-0/+13
2023-05-30cxl: Add functions to get an instance of / count regblocks of a given typeJonathan Cameron1-0/+3
2023-05-23cxl/mbox: Add background cmd handling machineryDavidlohr Bueso1-0/+8
2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams1-0/+1
2023-04-04cxl/port: Fix find_cxl_root() for RCDs and simplify itDan Williams1-2/+2
2023-04-04cxl/hdm: Skip emulation when driver manages mem_enableDan Williams1-1/+3
2023-02-25Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds1-2/+94
2023-02-14Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams1-2/+18
2023-02-14cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang1-1/+2
2023-02-14cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang1-1/+2
2023-02-14cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang1-0/+14
2023-02-14Merge branch 'for-6.3/cxl' into cxl/nextDan Williams1-0/+1
2023-02-14cxl: add RAS status unmasking for CXLDave Jiang1-0/+1
2023-02-10Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams1-0/+57
2023-02-10cxl/dax: Create dax devices for CXL RAM regionsDan Williams1-0/+12
2023-02-10tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams1-0/+2
2023-02-10cxl/region: Add region autodiscoveryDan Williams1-0/+29
2023-02-10cxl/region: Add a mode attribute for regionsDan Williams1-0/+14
2023-01-27driver core: make struct bus_type.uevent() take a const *Greg Kroah-Hartman1-2/+2
2023-01-26cxl/mem: Wire up event interruptsDavidlohr Bueso1-0/+4
2023-01-26cxl/mem: Read, trace, and clear events on driver loadIra Weiny1-0/+12
2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams1-0/+2
2022-12-05cxl: update names for interleave ways conversion macrosDave Jiang1-7/+7
2022-12-05cxl: update names for interleave granularity conversion macrosDave Jiang1-6/+7
2022-12-05Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams1-2/+9
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams1-9/+29
2022-12-05Merge branch 'for-6.2/cxl-security' into for-6.2/cxlDan Williams1-0/+11
2022-12-05cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_memDan Williams1-2/+0
2022-12-03cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield1-2/+9
2022-12-03cxl/pci: Add (hopeful) error handling supportDan Williams1-0/+1
2022-12-03cxl/pci: Find and map the RAS Capability StructureDan Williams1-0/+19
2022-12-03cxl/pci: Prepare for mapping RAS Capability StructureDan Williams1-1/+3
2022-12-03cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams1-8/+6
2022-12-03cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter1-0/+16
2022-12-03cxl/region: Manage CPU caches relative to DPA invalidation eventsDan Williams1-0/+8
2022-12-02cxl: add dimm_id support for __nvdimm_create()Dave Jiang1-0/+3
2022-12-02cxl/acpi: Move rescan to the workqueueDan Williams1-1/+2
2022-12-02cxl/pmem: Remove the cxl_pmem_wq and related infrastructureDan Williams1-17/+0
2022-12-02cxl/pmem: Refactor nvdimm device registration, delete the workqueueDan Williams1-2/+5
2022-12-02cxl/region: Drop redundant pmem region release handlingDan Williams1-1/+0
2022-11-14cxl: Replace HDM decoder granularity magic numbersAdam Manzanares1-4/+7
2022-11-14cxl/core: Remove duplicate declaration of devm_cxl_iomap_block()Robert Richter1-2/+0
2022-11-04cxl/region: Fix 'distance' calculation with passthrough portsDan Williams1-0/+2
2022-11-04cxl/pmem: Fix cxl_pmem_region and cxl_memdev leakDan Williams1-1/+1
2022-08-05cxl/region: describe targets and nr_targets members of cxl_region_paramsBagas Sanjaya1-0/+2
2022-08-01cxl/acpi: Minimize granularity for x1 interleavesDan Williams1-0/+2
2022-08-01cxl/region: prevent underflow in ways_to_cxl()Dan Carpenter1-1/+1
2022-07-26cxl/region: Introduce cxl_pmem_region objectsDan Williams1-1/+35
2022-07-26cxl/pmem: Fix offline_nvdimm_bus() to offline by bridgeDan Williams1-0/+1
2022-07-26cxl/region: Add region driver boiler plateDan Williams1-0/+1
2022-07-25cxl/hdm: Commit decoder state to hardwareDan Williams1-1/+12
2022-07-25cxl/region: Program target listsDan Williams1-0/+2
2022-07-25cxl/region: Attach endpoint decodersDan Williams1-0/+20
2022-07-25cxl/acpi: Add a host-bridge index lookup mechanismDan Williams1-0/+2
2022-07-25cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams1-0/+11
2022-07-25cxl/region: Allocate HPA capacity to regionsDan Williams1-0/+2
2022-07-25cxl/region: Add interleave geometry attributesBen Widawsky1-0/+33
2022-07-25cxl/region: Add a 'uuid' attributeBen Widawsky1-0/+25
2022-07-21cxl/region: Add region creation supportBen Widawsky1-0/+18
generated by cgit 1.3-korg (git 2.53.0) at 2026-06-01 07:04:04 +0000