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| author | Conor Dooley <conor.dooley@microchip.com> | 2025-05-16 10:59:39 +0100 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2025-05-16 12:57:12 +0000 |
| commit | db8266017e0a703809c83453112c8d5ceb4f03af (patch) | |
| tree | c53bb6cfec0def2ba8b26d740e3533f4babb6f3d | |
| parent | 9a5f8c7a81cde01738d4fa25624669a3d6f859e3 (diff) | |
| download | pci-dt-bindings.tar.gz | |
dt-bindings: PCI: microchip,pcie-host: Fix DMA coherency propertydt-bindings
PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.
For some reason, instead of adding dma-noncoherent to the binding
the pointless, NOP, property dma-coherent was. Swap dma-coherent for
dma-noncoherent.
Fixes: 04aa999eb96fd ("dt-bindings: PCI: microchip,pcie-host: Allow dma-noncoherent")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Link: https://lore.kernel.org/r/20250516-datebook-senator-ff7a1c30cbd5@spud
| -rw-r--r-- | Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 1aadfdee868fc0..47b0bad690d5a3 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -50,7 +50,7 @@ properties: items: pattern: '^fic[0-3]$' - dma-coherent: true + dma-noncoherent: true ranges: minItems: 1 |