diff options
| -rw-r--r-- | queue-6.15/revert-drm-amd-display-fix-vupdate-offset-calculations-for-dcn401.patch | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/queue-6.15/revert-drm-amd-display-fix-vupdate-offset-calculations-for-dcn401.patch b/queue-6.15/revert-drm-amd-display-fix-vupdate-offset-calculations-for-dcn401.patch new file mode 100644 index 0000000000..b661f11a0e --- /dev/null +++ b/queue-6.15/revert-drm-amd-display-fix-vupdate-offset-calculations-for-dcn401.patch @@ -0,0 +1,94 @@ +From 0fc9635a801f6ba3a03ad2de6d46f4f3e2fdfed6 Mon Sep 17 00:00:00 2001 +From: Dillon Varone <Dillon.Varone@amd.com> +Date: Fri, 28 Mar 2025 12:56:39 -0400 +Subject: Revert "drm/amd/display: Fix VUpdate offset calculations for dcn401" + +From: Dillon Varone <Dillon.Varone@amd.com> + +commit 0fc9635a801f6ba3a03ad2de6d46f4f3e2fdfed6 upstream. + +This reverts commit fe45e2af4a22e569b35b7f45eb9f040f6fbef94f. + +Reason for revert: it causes stuttering in some usecases. + +Reviewed-by: Aric Cyr <aric.cyr@amd.com> +Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> +Signed-off-by: Roman Li <roman.li@amd.com> +Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +--- + drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 44 -------------- + drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 1 + drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c | 2 + 3 files changed, 1 insertion(+), 46 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +@@ -2646,47 +2646,3 @@ void dcn401_plane_atomic_power_down(stru + if (hws->funcs.dpp_root_clock_control) + hws->funcs.dpp_root_clock_control(hws, dpp->inst, false); + } +- +-/* +- * apply_front_porch_workaround +- * +- * This is a workaround for a bug that has existed since R5xx and has not been +- * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. +- */ +-static void apply_front_porch_workaround( +- struct dc_crtc_timing *timing) +-{ +- if (timing->flags.INTERLACE == 1) { +- if (timing->v_front_porch < 2) +- timing->v_front_porch = 2; +- } else { +- if (timing->v_front_porch < 1) +- timing->v_front_porch = 1; +- } +-} +- +-int dcn401_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx) +-{ +- const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing; +- struct dc_crtc_timing patched_crtc_timing; +- int vesa_sync_start; +- int asic_blank_end; +- int interlace_factor; +- +- patched_crtc_timing = *dc_crtc_timing; +- apply_front_porch_workaround(&patched_crtc_timing); +- +- interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1; +- +- vesa_sync_start = patched_crtc_timing.v_addressable + +- patched_crtc_timing.v_border_bottom + +- patched_crtc_timing.v_front_porch; +- +- asic_blank_end = (patched_crtc_timing.v_total - +- vesa_sync_start - +- patched_crtc_timing.v_border_top) +- * interlace_factor; +- +- return asic_blank_end - +- pipe_ctx->global_sync.dcn4x.vstartup_lines + 1; +-} +--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +@@ -109,5 +109,4 @@ void dcn401_detect_pipe_changes( + void dcn401_plane_atomic_power_down(struct dc *dc, + struct dpp *dpp, + struct hubp *hubp); +-int dcn401_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx); + #endif /* __DC_HWSS_DCN401_H__ */ +--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c ++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +@@ -73,7 +73,7 @@ static const struct hw_sequencer_funcs d + .init_sys_ctx = dcn20_init_sys_ctx, + .init_vm_ctx = dcn20_init_vm_ctx, + .set_flip_control_gsl = dcn20_set_flip_control_gsl, +- .get_vupdate_offset_from_vsync = dcn401_get_vupdate_offset_from_vsync, ++ .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, + .calc_vupdate_position = dcn10_calc_vupdate_position, + .apply_idle_power_optimizations = dcn401_apply_idle_power_optimizations, + .does_plane_fit_in_mall = NULL, |