diff options
| -rw-r--r-- | queue-6.15/riscv-uaccess-only-restore-the-csr_status-sum-bit.patch | 82 | ||||
| -rw-r--r-- | queue-6.15/series | 1 |
2 files changed, 83 insertions, 0 deletions
diff --git a/queue-6.15/riscv-uaccess-only-restore-the-csr_status-sum-bit.patch b/queue-6.15/riscv-uaccess-only-restore-the-csr_status-sum-bit.patch new file mode 100644 index 0000000000..40c82bbd67 --- /dev/null +++ b/queue-6.15/riscv-uaccess-only-restore-the-csr_status-sum-bit.patch @@ -0,0 +1,82 @@ +From 265d6aba165c500389c80d394ac247460c443ef5 Mon Sep 17 00:00:00 2001 +From: Cyril Bur <cyrilbur@tenstorrent.com> +Date: Mon, 2 Jun 2025 12:15:43 +0000 +Subject: riscv: uaccess: Only restore the CSR_STATUS SUM bit + +From: Cyril Bur <cyrilbur@tenstorrent.com> + +commit 265d6aba165c500389c80d394ac247460c443ef5 upstream. + +During switch to csrs will OR the value of the register into the +corresponding csr. In this case we're only interested in restoring the +SUM bit not the entire register. + +Signed-off-by: Cyril Bur <cyrilbur@tenstorrent.com> +Link: https://lore.kernel.org/r/20250522160954.429333-1-cyrilbur@tenstorrent.com +Co-developed-by: Alexandre Ghiti <alexghiti@rivosinc.com> +Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> +Fixes: 788aa64c01f1 ("riscv: save the SR_SUM status over switches") +Link: https://lore.kernel.org/r/20250602121543.1544278-1-alexghiti@rivosinc.com +Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +--- + arch/riscv/include/asm/processor.h | 2 +- + arch/riscv/kernel/asm-offsets.c | 6 +++--- + arch/riscv/kernel/entry.S | 9 +++++---- + 3 files changed, 9 insertions(+), 8 deletions(-) + +--- a/arch/riscv/include/asm/processor.h ++++ b/arch/riscv/include/asm/processor.h +@@ -103,7 +103,7 @@ struct thread_struct { + struct __riscv_d_ext_state fstate; + unsigned long bad_cause; + unsigned long envcfg; +- unsigned long status; ++ unsigned long sum; + u32 riscv_v_flags; + u32 vstate_ctrl; + struct __riscv_v_ext_state vstate; +--- a/arch/riscv/kernel/asm-offsets.c ++++ b/arch/riscv/kernel/asm-offsets.c +@@ -34,7 +34,7 @@ void asm_offsets(void) + OFFSET(TASK_THREAD_S9, task_struct, thread.s[9]); + OFFSET(TASK_THREAD_S10, task_struct, thread.s[10]); + OFFSET(TASK_THREAD_S11, task_struct, thread.s[11]); +- OFFSET(TASK_THREAD_STATUS, task_struct, thread.status); ++ OFFSET(TASK_THREAD_SUM, task_struct, thread.sum); + + OFFSET(TASK_TI_CPU, task_struct, thread_info.cpu); + OFFSET(TASK_TI_PREEMPT_COUNT, task_struct, thread_info.preempt_count); +@@ -347,8 +347,8 @@ void asm_offsets(void) + offsetof(struct task_struct, thread.s[11]) + - offsetof(struct task_struct, thread.ra) + ); +- DEFINE(TASK_THREAD_STATUS_RA, +- offsetof(struct task_struct, thread.status) ++ DEFINE(TASK_THREAD_SUM_RA, ++ offsetof(struct task_struct, thread.sum) + - offsetof(struct task_struct, thread.ra) + ); + +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -399,14 +399,15 @@ SYM_FUNC_START(__switch_to) + REG_S s11, TASK_THREAD_S11_RA(a3) + + /* save the user space access flag */ +- li s0, SR_SUM +- csrr s1, CSR_STATUS +- REG_S s1, TASK_THREAD_STATUS_RA(a3) ++ csrr s0, CSR_STATUS ++ REG_S s0, TASK_THREAD_SUM_RA(a3) + + /* Save the kernel shadow call stack pointer */ + scs_save_current + /* Restore context from next->thread */ +- REG_L s0, TASK_THREAD_STATUS_RA(a4) ++ REG_L s0, TASK_THREAD_SUM_RA(a4) ++ li s1, SR_SUM ++ and s0, s0, s1 + csrs CSR_STATUS, s0 + REG_L ra, TASK_THREAD_RA_RA(a4) + REG_L sp, TASK_THREAD_SP_RA(a4) diff --git a/queue-6.15/series b/queue-6.15/series index 935a7402a6..1144789949 100644 --- a/queue-6.15/series +++ b/queue-6.15/series @@ -260,3 +260,4 @@ x86-pkeys-simplify-pkru-update-in-signal-frame.patch s390-ptrace-fix-pointer-dereferencing-in-regs_get_kernel_stack_nth.patch io_uring-kbuf-flag-partial-buffer-mappings.patch io_uring-gate-req_f_isreg-on-s_anon_inode-as-well.patch +riscv-uaccess-only-restore-the-csr_status-sum-bit.patch |