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A machine learning accelerator core designed for energy-efficient AI at the edge.

ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks

Design files and associated documentation for Sonata PCB, part of the Sunburst Project

OpenTitan: Open source silicon root of trust

64-bit multicore Linux-capable RISC-V processor

Rsync-based OSX-like time machine for Linux, MacOS and BSD for atomic and resumable local and remote backups

Random instruction generator for RISC-V processor verification

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

Empowering everyone to build reliable and efficient software.

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Verilator open-source SystemVerilog simulator and lint system