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abejgonzalez/README.md

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  1. ucb-bar/chipyard ucb-bar/chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala 2.1k 807

  2. firesim firesim Public

    Forked from firesim/firesim

    FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation of RISC-V Systems (Rocket Chip, BOOM) in the Cloud

    Scala 1

  3. firechip firechip Public

    Forked from firesim/firechip

    Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

    C

  4. icenet icenet Public

    Forked from firesim/icenet

    Network components (NIC, Switch) for FireBox

    Scala

  5. coremarkpro-util-make-riscv coremarkpro-util-make-riscv Public

    Forked from ccelio/coremarkpro-util-make-riscv

    The utility files to port CoreMark-Pro to RISC-V.

    Makefile