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danielespo/README.md

Hi there 👋 I'm Daniel Espinosa Gonzalez

  • 🔭 I’m currently working on system architecture at PsiQuantum
  • 💬 Ask me about reasoning, logic, VLSI and FPGA
  • 🌱 I’m currently learning Haskell and OCaml to make a "rust-analyzer/expect-test" for cocotb/verilator
  • 🤔 I’m looking for help with functional programming and creating C bindings in haskell/OCaml
  • 📫 How to reach me: LinkedIn or carrier pigeon
  • ⚡ Fun fact: I am an archery gold medallist and love jiu-jitsu

https://danluu.com/why-hardware-development-is-hard/

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  1. Solving-SAT-in-FPGA-UCSB Solving-SAT-in-FPGA-UCSB Public

    Creating a hardware solver in Verilog and then uploading to FPGA and connecting to a PC to solve SAT problems.

    Jupyter Notebook 4 4

  2. RISCVFall2024 RISCVFall2024 Public

    RISC V Processor RTL code and Cadence Files

    SystemVerilog 1

  3. microwalksat microwalksat Public

    microwalksat

    C 1

  4. learnverilog.v learnverilog.v Public

    A verilog file containing all of the verilog syntax and common expressions.

    Verilog 3

  5. learnvhdl.vhd learnvhdl.vhd Public

    All of VHDL syntax

    VHDL 1

  6. time-encoded-SC-SNN time-encoded-SC-SNN Public

    Code for the paper of the same name.

    Jupyter Notebook