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Ghidra is a software reverse engineering (SRE) framework

Java 71,693 7,847 Updated Jul 31, 2026

Hog (HDL-on-git) is an open-source tool to manage FPGA projects on git

Tcl 67 6 Updated Jul 31, 2026

Apple Silicon device emulator. Basic Android support

C 22 Updated Jul 1, 2026

This repository present solution for the AMD Pervasive AI Developer Contest.

Jupyter Notebook 2 2 Updated Jul 31, 2024

Hardware implementation of the SHA-256 cryptographic hash function

Verilog 385 108 Updated Dec 15, 2025

PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Python 740 61 Updated Aug 1, 2026

Simple high-level synthesis of portable Verilog directly from idiomatic imperative Python for numerical/DSP-heavy applications. Not an HDL.

Python 32 1 Updated Jul 31, 2026

ESP32-Quad-nRF24L01-Plus-Jammer is an open-source project for controlling four nRF24L01+ modules from an ESP32. It enables multi-band 2.4GHz RF jamming and channel sweeping for Bluetooth, WiFi, BLE…

C++ 83 18 Updated May 23, 2025

RealTek RTL8188eus WiFi driver with monitor mode & frame injection support

C 1,149 455 Updated Feb 3, 2025

Hundreds of models & providers. One command to find what runs on your hardware.

Rust 31,016 1,887 Updated Jul 31, 2026

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

SystemVerilog 870 132 Updated Jul 21, 2026

Open source FPGA-based NIC and platform for in-network compute

Verilog 17 Updated May 22, 2024

FPGA board-level debugging and reverse-engineering tool

Tcl 45 9 Updated Mar 24, 2023

ThunderScope GitHub Repo

ANTLR 1,281 255 Updated Jul 16, 2026

artix-7 PCIe dev board

33 12 Updated Sep 27, 2017

nMigen support for Xilinx Zynq devices

Python 17 8 Updated Nov 5, 2022

kari is an arduino library designed for high performance, easy sensor integration, asynchronous tasks and task scheduling. Developed and maintained by Vincent Muriithi Karimi.

C++ 38 1 Updated Oct 24, 2025

display 8X8 matrix LED with FPGA

Verilog 1 2 Updated Jul 15, 2020

Generate top-level HDL and XDC IO constraints from validated YAML for Xilinx-based FPGA and MPSoC boards

Python 2 Updated Jul 1, 2026

RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.

C 111 27 Updated Dec 24, 2023

RTL implementation of the Nasdaq ITCH protocol decoder.

Verilog 9 7 Updated Nov 1, 2023

Open-source ESP32 firmware for a 1.28″ round display that shows live ADS-B aircraft around your location as a sonar-style plane radar.

C++ 850 187 Updated Jul 2, 2026

M.2 PCIe Artix 7 FPGA Accelerator Card

C 35 7 Updated Mar 17, 2025

System-level consistency checking for Linux SoC Device Trees

Python 13 1 Updated Jul 7, 2026

Simple Stepper Motor Turret controled by esp32

Python 3 1 Updated May 15, 2026

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Python 1,177 241 Updated Feb 26, 2026

Linux Wi-Fi driver for ESP chips

C 7 2 Updated Jun 12, 2026

verilog example to drive PCM5102 DAC with FPGA

C 19 4 Updated Apr 30, 2018
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