modules: add west patches for Corstone-1000-A320 support

Add west patches for external modules not yet updated in their
Zephyr mirrors:

- TF-M: DSU-120T PPU driver
  PR: zephyrproject-rtos/trusted-firmware-m#172

- TF-A: Cortex-A320 support (GICv3, MPIDR layout,
  Ethos-U85/SRAM mappings, multicore hold pen)
  PR: zephyrproject-rtos/trusted-firmware-a#8

- TF-A: Secondary core hold pen cache coherency fix
  (pending upstream)

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Author: Nicolas Pitre

zephyr/patches.yml

@@ -0,0 +1,46 @@
+patches:
+  - path: 0001-plat-corstone1000-Add-support-for-Cortex-A320-varian.patch
+    sha256sum: d47d16316c0c16f9699dd0ef9f2bd8dd54cf35e8024023d48ba2769d69f1fa84
+    module: trusted-firmware-m
+    apply-command: git am
+    author: Harsimran Singh Tungal
+    email: harsimransingh.tungal@arm.com
+    date: 2025-07-29
+    upstreamable: true
+    merge-pr: https://github.com/zephyrproject-rtos/trusted-firmware-m/pull/172
+    comments: |
+      Add DSU-120T PPU driver for Cortex-A320 host power-on.
+      Required to boot the host CPU on the Corstone-1000-A320 FVP.
+      Upstream: https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/45749
+
+  - path: 0002-feat-corstone-1000-add-Cortex-A320-support.patch
+    sha256sum: 8c2c165dea44019ea5d12036543e302322bef3bd1916678d0caed25cb6099e5e
+    module: trusted-firmware-a
+    apply-command: git am
+    author: Harsimran Singh Tungal
+    email: harsimransingh.tungal@arm.com
+    date: 2025-11-27
+    upstreamable: true
+    merge-pr: https://github.com/zephyrproject-rtos/trusted-firmware-a/pull/8
+    comments: |
+      Add Cortex-A320 support to TF-A for Corstone-1000.
+      Introduces CORSTONE1000_CORTEX_A320 build flag, GICv3 with GIC-600,
+      A320 MPIDR layout, Ethos-U85 and non-secure SRAM mappings, and
+      multicore hold pen for SMP secondary core bring-up.
+      Upstream: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/45729
+
+  - path: 0003-fix-corstone1000-fix-secondary-core-hold-pen-cache-c.patch
+    sha256sum: 2c37c1746bb18b3c851a9257b33d98b26fb56dfae29ec52e3c7251abbcb7f30a
+    module: trusted-firmware-a
+    apply-command: git am
+    author: Nicolas Pitre
+    email: npitre@baylibre.com
+    date: 2026-02-12
+    upstreamable: true
+    comments: |
+      Fix secondary core hold pen cache coherency issue.
+      BL2's cache flush during BL2-to-BL31 transition pushes stale cached
+      data over the WAIT values that secondary CPUs wrote from non-cached
+      context. Fix by cache-line-aligning hold slots (64-byte stride),
+      moving hold base past FW_CONFIG area, and having pwr_domain_on
+      explicitly write all slots before flushing.