feat(corstone-1000): add Cortex-A320 support#8
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npitre wants to merge 1 commit intozephyrproject-rtos:masterfrom
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feat(corstone-1000): add Cortex-A320 support#8npitre wants to merge 1 commit intozephyrproject-rtos:masterfrom
npitre wants to merge 1 commit intozephyrproject-rtos:masterfrom
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Introduce `CORSTONE1000_CORTEX_A320` to enable Cortex-A320 on Corstone-1000 while keeping Cortex-A35 as the default. When the define is enabled, the build switches from `cortex_a35.S` to `cortex_a320.S`, maintaining compatibility with existing A35-based designs. Also add Normal-World mappings for the Ethos-U85 NPU and its SRAM on Cortex-A320 platforms so U-Boot and other non-secure software can safely access these regions: * **Ethos-U85 registers**: base `0x1A050000`, size `0x00004000` (16 KB), attrs `MT_DEVICE | MT_RW | MT_NS` * **Non-secure SRAM**: base `0x02400000`, size `0x00400000` (4 MB), attrs `MT_MEMORY | MT_RW | MT_NS` Enable GICv3 with GIC-600 when building for Cortex-A320 (retain GICv2/GIC-400 for Cortex-A35): * Update `plat_my_core_pos()` and `plat_arm_calc_core_pos()` to use the Cortex-A320 MPIDR_EL1 affinity layout. * Add an A320-specific core-position routine in assembly guarded by `CORSTONE1000_CORTEX_A320`. * Switch to the GICv3 driver with GIC-600 extensions: update GIC base addresses, use GICv3 APIs, and set `USE_GIC_DRIVER=3`, `GICV3_SUPPORT_GIC600=1`, `GIC_ENABLE_V4_EXTN=1`. These changes prepare the platform for Cortex-A320 integration and ensure correct GIC configuration and secondary-core bring-up, while preserving A35 behavior. Change-Id: Ief03dd528e67918e160d5b42ad1344b0ba3440f8 Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> Signed-off-by: Frazer Carsley <frazer.carsley@arm.com> Signed-off-by: Michael Safwat <michael.safwat@arm.com> (cherry picked from commit 25148ce)
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Feb 19, 2026
Add west patches for external modules not yet updated in their Zephyr mirrors: - TF-M: DSU-120T PPU driver PR: zephyrproject-rtos/trusted-firmware-m#172 - TF-A: Cortex-A320 support (GICv3, MPIDR layout, Ethos-U85/SRAM mappings, multicore hold pen) PR: zephyrproject-rtos/trusted-firmware-a#8 - TF-A: Secondary core hold pen cache coherency fix (pending upstream) Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
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Feb 23, 2026
Point west.yml TF-M and TF-A revisions to their respective Zephyr mirror PRs that add Cortex-A320 support: - TF-M: DSU-120T PPU driver for Cortex-A320 host power-on PR: zephyrproject-rtos/trusted-firmware-m#172 - TF-A: Cortex-A320 support (GICv3, MPIDR layout, Ethos-U85/SRAM mappings, multicore hold pen) PR: zephyrproject-rtos/trusted-firmware-a#8 Add west patch for TF-A secondary core hold pen cache coherency fix (pending upstream review): https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/48505 Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
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Feb 27, 2026
Point west.yml TF-M and TF-A revisions to add Cortex-A320 support: - TF-M: DSU-120T PPU driver for Cortex-A320 host power-on (merged) zephyrproject-rtos/trusted-firmware-m#172 - TF-A: Cortex-A320 support (GICv3, MPIDR layout, Ethos-U85/SRAM mappings, multicore hold pen) PR: zephyrproject-rtos/trusted-firmware-a#8 Add west patch for TF-A generic hold pen with cache coherency fix (upstream review): https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/48636 https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/48505 https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/48637 https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/48638 Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
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Cherry-pick of upstream TF-A commit 25148ce
to the Zephyr mirror.
This adds:
CORSTONE1000_CORTEX_A320build option to switch from Cortex-A35 to Cortex-A320Required by the Zephyr Corstone-1000-A320 FVP board support:
zephyrproject-rtos/zephyr#104035