Hardware and Computer Systems Engineer
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University of Ioannina
- Ioannina, Greece
- dreamxlabs.gr
- @pantelisEVs
- in/patsaoglou-pantelis
- https://dreamxlabs.gr/contact
Highlights
- Pro
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JTAG-IEEE-1149.1
JTAG-IEEE-1149.1 PublicBasic JTAG standard implementation in Verilog and integration with a CUT
Verilog 4
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meta-st-thingscore
meta-st-thingscore PublicYocto meta layer for the DreamXLabs ThingsCore-1 SOM
BitBake 5
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