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1. openhwgroup/cvw openhwgroup/cvw Public

   CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

   SystemVerilog 484 370

2. CharLib CharLib Public

   Open-source repository for a standard-cell library characterizer using complete open-source tools

   Python 45 16

3. globalfoundries-pdk-libs-gf180mcu_osu_sc globalfoundries-pdk-libs-gf180mcu_osu_sc Public

   Forked from google/globalfoundries-pdk-libs-gf180mcu_osu_sc

   Digital standard cells for GF180MCU provided by Oklahoma State University.

   HTML 8 4

4. Drop-In-JTAG Drop-In-JTAG Public

   Open Source Silicon Development Testing Unit using JTAG

   SystemVerilog 5 1

5. sky130_cds sky130_cds Public

   This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit

   Tcl 29 3

6. SpringerBookArith04 SpringerBookArith04 Public

   These are files from my 2004 book, "Digital Computer Arithmetic Datapath Design Using Verilog HDL"

   Verilog 2