STM32 SPI: Make full use of FIFOs for H7-compatible#103079
Merged
fabiobaltieri merged 6 commits intozephyrproject-rtos:mainfrom Feb 17, 2026
Merged
STM32 SPI: Make full use of FIFOs for H7-compatible#103079fabiobaltieri merged 6 commits intozephyrproject-rtos:mainfrom
fabiobaltieri merged 6 commits intozephyrproject-rtos:mainfrom
Conversation
zephyrbot
added
platform: STM32
zephyrbot
requested review from
FRASTM,
GeorgeCGV,
JarmouniA,
decsny,
djiatsaf-st,
erwango,
etienne-lms,
juickar,
mathieuchopstm,
nashif,
tbursztyka and
teburd
gautierg-st
force-pushed
the
spi_h7_fifo
branch
2 times, most recently
from
a4fd230 to
6b2330f
Compare
etienne-lms
reviewed
Feb 2, 2026
gautierg-st
force-pushed
the
spi_h7_fifo
branch
2 times, most recently
from
a6d603b to
4542c0b
Compare
etienne-lms
reviewed
Feb 2, 2026
Contributor
etienne-lms
left a comment
etienne-lms
left a comment
There was a problem hiding this comment.
LGTM with a few nitpicking comments.
gautierg-st
force-pushed
the
spi_h7_fifo
branch
2 times, most recently
from
f0a4c0c to
be0af18
Compare
etienne-lms
previously approved these changes
Feb 3, 2026
gautierg-st
dismissed stale reviews from mathieuchopstm and etienne-lms
via
7b3175f
gautierg-st
force-pushed
the
spi_h7_fifo
branch
from
be0af18 to
7b3175f
Compare
Contributor
Author
|
Rebase done |
erwango
previously approved these changes
Feb 6, 2026
mathieuchopstm
previously approved these changes
Feb 9, 2026
Comment on lines
+590
to
+592
| #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) | ||
| return spi_stm32_shift_fifo(cfg, data); | ||
| #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */ |
Contributor
There was a problem hiding this comment.
This looks a bit weird - at first glance, one could think it's a no-op if cfg->fifo_enabled == true but !DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) (I assume this can never happen though, hence not an issue)
Contributor
Author
There was a problem hiding this comment.
Correct! At the moment, the fifo-enable property is only available for st,stm32h7-spi instances.
So cfg->fifo_enabled cannot be true for other instances.
Member
|
@tbursztyka PTAL |
Until now, SPI DMA transfers were not possible for H7-compatible STM32 devices if the fifo-enable property was enabled. This commit adds the support of this property with DMA usage. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit adds the support of the FIFO threshold for H7-compatible SPI. This makes full use of the two FIFOs (Tx and Rx) available for these devices, by packing the frames together in a single read or write when possible, reducing the number of operations. The FIFO threshold is supported only when fifo-enabled property is enabled in device tree. This new implementation is useful in interrupt mode at fast speed: on Nucleo H753ZI, test_spi_complete_multiple_timed at fast speed indicates a theoretical minimum duration of 27 µs, with a latency measurement of 18 µs for the new code against 34 µs previously, and a huge 76 µs when fifo-enable is not present. There are no noticeable changes at slow speed, or in polling or DMA mode. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add the fifo-enable property to the overlays with the st,stm32h7-spi compatible so that they it is tested on test bench. Also slightly increase the latency tolerance for Nucleo G071RB. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For an asynchronous transfer, the driver was waiting until transfer was ended to leave the transceive function, which defeated the purpose of async. Restore previous behavior. The transfer is still blocking for half duplex though. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add two FIFO related properties for the st,stm32h7-spi bindings: - Size of the FIFO - Maximal size of the transfer when fifo-enable property is used Also fill all dtsi files that require the new properties. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new SPI FIFO related property to retrieve FIFO size (instead of guessing it from the supported data width), and to check that the TSIZE register is not written with a value that exceeds the maximal supported transfer size. Also reorder the spi_stm32_config structure to have better packing. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
gautierg-st
dismissed stale reviews from mathieuchopstm and erwango
via
3743917
gautierg-st
force-pushed
the
spi_h7_fifo
branch
from
7b3175f to
3743917
Compare
Contributor
Author
|
Rebased to fix conflicts |
|
erwango
approved these changes
Feb 13, 2026
Member
|
@tbursztyka Any chance you have a look soon ? |
etienne-lms
approved these changes
Feb 13, 2026
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
9 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
This PR introduces some changes to the STM32 SPI driver to fully use the TX and RX FIFOs that can be found on devices with the
st,stm32h7-spicompatible. Instead of sending and receiving data byte per byte, the driver sends or reads them by larger packets (size of the packet depends on FIFO size). This reduces the number of operations necessary to transfer all data and improves performance.