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dts: QEMU: Add i/d-cache-line-size properties#104724

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JarmouniA wants to merge 2 commits intozephyrproject-rtos:mainfrom
JarmouniA:add_qemu_dts_cache_line_size
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dts: QEMU: Add i/d-cache-line-size properties#104724
JarmouniA wants to merge 2 commits intozephyrproject-rtos:mainfrom
JarmouniA:add_qemu_dts_cache_line_size

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Add i/d-cache-line-size dts properties for qemu virt-a53 and cortex-a9 targets.

Add L1 I/DCache line size to CPU node

Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Add L1 I/DCache line size to CPU node

Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
@JarmouniA JarmouniA marked this pull request as ready for review March 1, 2026 18:21
@zephyrbot zephyrbot added area: Boards/SoCs area: ARM64 ARM (64-bit) Architecture labels Mar 1, 2026
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area: ARM64 ARM (64-bit) Architecture area: Boards/SoCs

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