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stm32 xspi driver supports clock domain and DMA#73220

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nashif merged 3 commits intozephyrproject-rtos:mainfrom
FRASTM:xspi_multi
Jun 12, 2024
Merged

stm32 xspi driver supports clock domain and DMA#73220
nashif merged 3 commits intozephyrproject-rtos:mainfrom
FRASTM:xspi_multi

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@FRASTM FRASTM commented May 23, 2024

Adapt the drivers/flash/flash_stm32_xspi driver to support several clock domain definition and dma transfer

  • Change the clock configuration to configure several clocks with pclken[]

where the &xspi node has

clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00100000>,
		<&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>;
  • add the DMA transfer on DMA channels to read and write data to the external NOR flash
&xspi1 {
       /* request 57 for XSPI1 */
	dmas = <&gpdma1 4 57 STM32_DMA_PERIPH_TX
		&gpdma1 5 57 STM32_DMA_PERIPH_RX>;
	dma-names = "tx", "rx";
};
@FRASTM FRASTM force-pushed the xspi_multi branch 2 times, most recently from d4816df to 6650084 Compare May 23, 2024 14:45
@FRASTM FRASTM changed the title makes the stm32 xspi driver multi-instantiable May 28, 2024
@FRASTM FRASTM changed the title stm32 xspi driver supports cock domain and DMA May 28, 2024
@FRASTM FRASTM requested a review from gautierg-st May 28, 2024 14:13
@FRASTM FRASTM force-pushed the xspi_multi branch 3 times, most recently from 4fdaf86 to 8338dfe Compare May 29, 2024 09:34
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FRASTM commented May 29, 2024

CI failure : west build -p auto -b nrf54h20dk/nrf54h20/cpuapp samples/drivers/spi_flash due to #73005

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FRASTM commented Jun 3, 2024

CI requires the commit a555cbdbc24f9819512ab8dc13a2d063f11d1e0a
--> Waiting for merge of the PR #73027

@FRASTM FRASTM marked this pull request as ready for review June 10, 2024 11:51
@FRASTM FRASTM requested review from ABOSTM and erwango as code owners June 10, 2024 11:51
@FRASTM FRASTM requested a review from gautierg-st June 10, 2024 12:15
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Update log message. Otherwise LGTM

@ajarmouni-st ajarmouni-st removed the request for review from ABOSTM June 10, 2024 12:57
FRASTM added 3 commits June 11, 2024 08:51
Configure the xspi clocks domain by the clock domain
as defined by the DTS
Up to 3 possible clock confg : xspix, xspi_ker, xspi_mgr

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the commands to read and write to/from the xSPI with gpDMA
On the stm32h5 device, the one request for xspi instance

Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32 xspi node is another possible multi-spi for connecting
with gpDMA channels for Rx and Tx, same request.
Channels 4 and 5 are preferred for AHB periph to/from ext. Mem.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
@erwango erwango assigned erwango and unassigned kartben Jun 11, 2024
@nashif nashif merged commit b04cd03 into zephyrproject-rtos:main Jun 12, 2024
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6 participants