299 questions
Advice
1
vote
1
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107
views
Are VMX instructions (vmcall, vmlaunch, vmresume, vmxoff) implemented in gem5 x86?
I am currently trying to do some hypervisor research using gem5 for a time-accurate simulation of the hardware. I have encountered in the gem5/src/arch/x86/isa/decoder/two_byte_opcodes.isa a case
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- 477
0
votes
0
answers
526
views
How to run Android 13+ (aosp-arm64) on QEMU without Cuttlefish?
I have been trying to run a self-compiled AOSP build in QEMU. I have successfully compiled the AOSP source code for android-13.0.0_r84 (target aosp_arm64-eng) and obtained the following image files:
...
- 1
0
votes
1
answer
64
views
EL1 to EL0 exception hangs in qemu while simulating svc trap
I have below assembly code and I am trying to trap svc exception, however the code just hangs
.global _start
.section .text
_start:
// --- Setup EL1 stack ---
ldr x0, =_el1_stack_top
mov ...
- 1,598
0
votes
1
answer
110
views
How to debug QEMU live migration with GDB without causing the destination VM to hang?
I'm trying to debug the QEMU source code to track dirty page updates during live migration. My goal is to inspect the behavior inside functions like cpu_physical_memory_set_dirty_lebitmap() on the ...
3
votes
0
answers
57
views
How to know the interrupt ID which is signaled currently without acknowledging it?
I'm working on a hypervisor on ARMv8 (GICv3), which runs one host VM and one guest VM.
Host VM does not support a virtual GIC, but guest VMs have vGIC support.
To support this hybrid model where vGIC ...
- 12.8k
1
vote
0
answers
86
views
disabling HW-prefetcher on an android Pixel 8
I am writing a kernel module which makes some low level experiments, and I've noticed that the HW prefetcher is intrupting them. I want to disable it while the experiemnts run.
I am running on Pixel 8 ...
0
votes
1
answer
83
views
XEN compilation binary for x86_64 platform always result ELF 32-bit LSB executable
For experiment, I simulate x86_64 architecture using qemu-system-x86_64 on top of x86_64 based host machine (Ubuntu 22.04). Next I want to boot with Xen binary.
However when I compile Xen hypervisor ...
- 469
1
vote
0
answers
35
views
Why don't I get the correct function RVA from the PE export table in my loader code?
I'm writing a minimal PE loader that parses the export table to locate functions by name, in my hypervisor. However, when I try to retrieve the RVA of a function, the value seems incorrect. Here's the ...
1
vote
0
answers
105
views
Trying to make 10 VMs in Windows Hypervisor getting "Import-VM : The file 'G:\VM\New Machine.vhdx' already exists." and a couple other errors
I am trying to make 19 copies of a VM (will be used for testing)
PowerShell is outside of my area of expertise but put this together with a modest about of research and ChatGPT. Unfortuatley I have ...
- 13
0
votes
0
answers
63
views
Running powershell for VM checkpoint restore via double clicking a batch file or .ps1 file
Afternoon. I'm new new to this and trying to expand my knowledge so forgive me if I sound way off from left field.
I have a PC running a VM that I use to teach students some of our software install in ...
1
vote
1
answer
317
views
Intel VT-x: How do I trigger posted interrupt processing on the same core?
I'm struggling to fully understand the posted interrupt processing feature in Intel VT-x. Ignoring VT-d for the moment, as a first baby step I am just trying to get CPU based posted interrupt delivery ...
- 162
0
votes
1
answer
159
views
QEMU/virt64 vGIC dist and CPU interface addresses
I'm working with QEMU/virt64 (armv8) and I've a question related to an IRQ injection from my hypervisor running in EL2 mode.
First, is it correct that the vGIC distributor address is 0x08000000, i.e. ...
0
votes
0
answers
67
views
2D page walk using EPT
EPT extension defines a base register that points to level 4 page table of the hypervisor (host physical address).
When a TLB miss occurs, the page table walker takes 20 memory accesses to translate a ...
- 139
1
vote
1
answer
69
views
Why does the VMCS ES selector have a index of 0 instead of 3?
I found that the ES selector field is 0x0800 but shouldn’t it be 0x0806 since it’s the 3rd index in the list CS, SS, DS, ES, FS, GS, LDTR, TR
I got the selector list from Volume 3C: System Programming ...
- 13
0
votes
1
answer
374
views
Can the hypervisor and AMD SEV VMs share memory?
I was wondering if modifying the KVM would allow the hypervisor and VM to share memory.
I've been studying SEV, AMD's memory encryption technology, and this question came up.
Is it possible for the ...
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