diff options
| author | Mark Brown <broonie@kernel.org> | 2026-05-29 18:08:44 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-05-29 18:08:44 +0100 |
| commit | e2e1d5f8a454d6f34e52aa88fd8500ca61deeaf4 (patch) | |
| tree | c3da0242551264129bd52115191ed426d6bca91e /arch | |
| parent | 39a7f940bec375e9f2f08ea3bf1cbe7c58ca0646 (diff) | |
| parent | 11883fdc73a1c123f795be3cc0f512aee0c49d1e (diff) | |
| download | linux-next-history-e2e1d5f8a454d6f34e52aa88fd8500ca61deeaf4.tar.gz | |
Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git
Diffstat (limited to 'arch')
23 files changed, 641 insertions, 150 deletions
diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index c6babc8ad2ba6..46dea445742b2 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -42,6 +42,17 @@ }; + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <13000000>; + arm,cpu-registers-not-fw-configured; + }; + clocks { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi index 71ac2b94c6ba3..aa42377b47da6 100644 --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -249,7 +249,7 @@ #reset-cells = <1>; }; - pio: pinctrl@10005000 { + pio: pinctrl@1000b000 { compatible = "mediatek,mt7623-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; @@ -1017,14 +1017,14 @@ }; &pio { - cir_pins_a:cir-default { + cir_pins_a: cir-default-pins { pins-cir { pinmux = <MT7623_PIN_46_IR_FUNC_IR>; bias-disable; }; }; - i2c0_pins_a: i2c0-default { + i2c0_pins_a: i2c0-default-pins { pins-i2c0 { pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>, <MT7623_PIN_76_SCL0_FUNC_SCL0>; @@ -1032,40 +1032,40 @@ }; }; - i2c1_pins_a: i2c1-default { - pin-i2c1 { + i2c1_pins_a: i2c1-default-pins { + pins-i2c1 { pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>, <MT7623_PIN_58_SCL1_FUNC_SCL1>; bias-disable; }; }; - i2c1_pins_b: i2c1-alt { - pin-i2c1 { + i2c1_pins_b: i2c1-alt-pins { + pins-i2c1 { pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>, <MT7623_PIN_243_UCTS2_FUNC_SDA1>; bias-disable; }; }; - i2c2_pins_a: i2c2-default { - pin-i2c2 { + i2c2_pins_a: i2c2-default-pins { + pins-i2c2 { pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>, <MT7623_PIN_78_SCL2_FUNC_SCL2>; bias-disable; }; }; - i2c2_pins_b: i2c2-alt { - pin-i2c2 { + i2c2_pins_b: i2c2-alt-pins { + pins-i2c2 { pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>, <MT7623_PIN_123_HTPLG_FUNC_SCL2>; bias-disable; }; }; - i2s0_pins_a: i2s0-default { - pin-i2s0 { + i2s0_pins_a: i2s0-default-pins { + pins-i2s0 { pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>, <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>, <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>, @@ -1076,8 +1076,8 @@ }; }; - i2s1_pins_a: i2s1-default { - pin-i2s1 { + i2s1_pins_a: i2s1-default-pins { + pins-i2s1 { pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>, <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>, <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>, @@ -1088,7 +1088,7 @@ }; }; - key_pins_a: keys-alt { + key_pins_a: keys-alt-pins { pins-keys { pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>, <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ; @@ -1096,7 +1096,7 @@ }; }; - led_pins_a: leds-alt { + led_pins_a: leds-alt-pins { pins-leds { pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>, <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>, @@ -1104,7 +1104,7 @@ }; }; - mmc0_pins_default: mmc0default { + mmc0_pins_default: mmc0-default-pins { pins-cmd-dat { pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, @@ -1130,7 +1130,7 @@ }; }; - mmc0_pins_uhs: mmc0 { + mmc0_pins_uhs: mmc0-uhs-pins { pins-cmd-dat { pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, @@ -1158,7 +1158,7 @@ }; }; - mmc1_pins_default: mmc1default { + mmc1_pins_default: mmc1-default-pins { pins-cmd-dat { pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, @@ -1188,7 +1188,7 @@ }; }; - mmc1_pins_uhs: mmc1 { + mmc1_pins_uhs: mmc1-uhs-pins { pins-cmd-dat { pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, @@ -1207,7 +1207,7 @@ }; }; - nand_pins_default: nanddefault { + nand_pins_default: nand-default-pins { pins-ale { pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>; drive-strength = <8>; @@ -1236,15 +1236,15 @@ }; }; - pcie_default: pcie_pin_default { - pins_cmd_dat { + pcie_default: pcie-default-pins { + pins-cmd-dat { pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>, <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>; bias-disable; }; }; - pwm_pins_a: pwm-default { + pwm_pins_a: pwm-default-pins { pins-pwm { pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, <MT7623_PIN_204_PWM1_FUNC_PWM1>, @@ -1254,7 +1254,7 @@ }; }; - spi0_pins_a: spi0-default { + spi0_pins_a: spi0-default-pins { pins-spi { pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>, <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>, @@ -1264,7 +1264,7 @@ }; }; - spi1_pins_a: spi1-default { + spi1_pins_a: spi1-default-pins { pins-spi { pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>, <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>, @@ -1273,7 +1273,7 @@ }; }; - spi2_pins_a: spi2-default { + spi2_pins_a: spi2-default-pins { pins-spi { pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>, <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>, @@ -1282,28 +1282,28 @@ }; }; - uart0_pins_a: uart0-default { + uart0_pins_a: uart0-default-pins { pins-dat { pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>, <MT7623_PIN_80_UTXD0_FUNC_UTXD0>; }; }; - uart1_pins_a: uart1-default { + uart1_pins_a: uart1-default-pins { pins-dat { pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>, <MT7623_PIN_82_UTXD1_FUNC_UTXD1>; }; }; - uart2_pins_a: uart2-default { + uart2_pins_a: uart2-default-pins { pins-dat { pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>, <MT7623_PIN_15_GPIO15_FUNC_UTXD2>; }; }; - uart2_pins_b: uart2-alt { + uart2_pins_b: uart2-alt-pins { pins-dat { pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>, <MT7623_PIN_201_UTXD2_FUNC_UTXD2>; diff --git a/arch/arm/boot/dts/mediatek/mt8135.dtsi b/arch/arm/boot/dts/mediatek/mt8135.dtsi index 0f291ad22d3af..b03bd980ec375 100644 --- a/arch/arm/boot/dts/mediatek/mt8135.dtsi +++ b/arch/arm/boot/dts/mediatek/mt8135.dtsi @@ -148,7 +148,7 @@ * Pinctrl access register at 0x10005000 and 0x1020c000 through * regmap. Register 0x1000b000 is used by EINT. */ - pio: pinctrl@10005000 { + pio: pinctrl@1000b000 { compatible = "mediatek,mt8135-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 387faa9c2a09b..a86fb313b1a9d 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -47,6 +47,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-4e.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn13.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn14.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn15.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn18.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-emmc.dtbo @@ -70,18 +72,24 @@ mt7988a-bananapi-bpi-r4-2g5-sd-dtbs := \ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5-sd.dtb mt7988a-bananapi-bpi-r4-pro-8x-emmc-dtbs := \ mt7988a-bananapi-bpi-r4-pro-8x.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \ + mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \ mt7988a-bananapi-bpi-r4-pro-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-emmc.dtb mt7988a-bananapi-bpi-r4-pro-8x-sd-dtbs := \ mt7988a-bananapi-bpi-r4-pro-8x.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \ + mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \ mt7988a-bananapi-bpi-r4-pro-sd.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15-dtbs := \ mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \ mt7988a-bananapi-bpi-r4-pro-cn15.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15.dtb mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18-dtbs := \ mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \ mt7988a-bananapi-bpi-r4-pro-cn18.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi index 45ad69ee49edd..a953fb527b69b 100644 --- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -164,15 +164,8 @@ regulator-min-microvolt = <900000>; regulator-max-microvolt = <1300000>; }; - mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt { - regulator-name = "vcn33_1_bt"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; - }; - mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi { - regulator-name = "vcn33_1_wifi"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; + mt6359_vcn33_1_ldo_reg: ldo_vcn33_1 { + regulator-name = "vcn33_1"; }; mt6359_vaux18_ldo_reg: ldo_vaux18 { regulator-name = "vaux18"; @@ -231,15 +224,8 @@ regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; }; - mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt { - regulator-name = "vcn33_2_bt"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; - }; - mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi { - regulator-name = "vcn33_2_wifi"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; + mt6359_vcn33_2_ldo_reg: ldo_vcn33_2 { + regulator-name = "vcn33_2"; }; mt6359_va12_ldo_reg: ldo_va12 { regulator-name = "va12"; diff --git a/arch/arm64/boot/dts/mediatek/mt6365.dtsi b/arch/arm64/boot/dts/mediatek/mt6365.dtsi new file mode 100644 index 0000000000000..8d16f53c8c6bb --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6365.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2026 MediaTek Inc. + */ + +#include "mt6359.dtsi" + +&pmic { + compatible = "mediatek,mt6365", "mediatek,mt6359"; + + mt6365regulators: regulators { + compatible = "mediatek,mt6365-regulator", "mediatek,mt6359-regulator"; + }; +}; + +&pmic_adc { + compatible = "mediatek,mt6365-auxadc", "mediatek,mt6359-auxadc"; +}; + +mt6365codec: &mt6359codec { + compatible = "mediatek,mt6365-codec", "mediatek,mt6359-codec"; +}; + +mt6365rtc: &mt6359rtc { + compatible = "mediatek,mt6365-rtc", "mediatek,mt6358-rtc"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts b/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts index a314c3e05e500..db399cb3ead73 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include "mt7981b.dtsi" @@ -12,4 +15,37 @@ reg = <0 0x40000000 0 0x10000000>; device_type = "memory"; }; + + keys { + compatible = "gpio-keys"; + + key-mesh { + label = "MESH"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_9>; + linux,input-type = <EV_SW>; + }; + + key-reset { + label = "RESET"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_STATUS; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 1bbe219380f99..e63ba3ae395e9 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -150,6 +150,21 @@ #clock-cells = <1>; }; + crypto@10320000 { + compatible = "mediatek,mt7981-crypto", + "inside-secure,safexcel-eip97ies"; + reg = <0 0x10320000 0 0x40000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <&topckgen CLK_TOP_EIP97B>; + clock-names = "core"; + assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x100>; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso new file mode 100644 index 0000000000000..973b76ba0cbfb --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Frank Wunderlich <frank-w@public-files.de> + */ + +/* This enables key-m slot CN13 on pcie2(11280000 1L0) on BPI-R4-Pro */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a"; +}; + +&{/soc/pinctrl@1001f000/pcie-2-hog} { + output-high; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso new file mode 100644 index 0000000000000..90b2a64459c31 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Frank Wunderlich <frank-w@public-files.de> + */ + +/* This enables key-m slot CN14 on pcie3(11290000 1L1) on BPI-R4-Pro */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a"; +}; + +&{/soc/pinctrl@1001f000/pcie-3-hog} { + output-high; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi index a48132f094114..1eeb72108b9b7 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi @@ -61,14 +61,14 @@ led_red: sys-led-red { color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; gpios = <&pca9555 15 GPIO_ACTIVE_HIGH>; - default-state = "on"; }; led_blue: sys-led-blue { color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_ACTIVITY; gpios = <&pca9555 14 GPIO_ACTIVE_HIGH>; - default-state = "on"; }; }; @@ -185,13 +185,6 @@ status = "okay"; }; -&fan { - pinctrl-0 = <&pwm0_pins>; - pinctrl-names = "default"; - pwms = <&pwm 0 50000>; - status = "okay"; -}; - &gmac0 { status = "okay"; }; @@ -207,7 +200,7 @@ }; &gsw_port0 { - label = "mgmt"; + label = "lan5"; }; /* R4Pro has only port 0 connected, so disable the others */ @@ -437,14 +430,12 @@ pcie-2-hog { gpio-hog; gpios = <79 GPIO_ACTIVE_HIGH>; - output-high; }; /* 1L1 0=key-b (CN18), 1=key-m (CN14) */ pcie-3-hog { gpio-hog; gpios = <63 GPIO_ACTIVE_HIGH>; - output-high; }; pwm0_pins: pwm0-pins { diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi index b495a241b4432..0250b4eeadd45 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi @@ -73,6 +73,10 @@ pmic@6 { compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator"; reg = <0x6 SPMI_USID>; + pvdd1-supply = <&pp4200_z2>; + pvdd2-supply = <&pp4200_z2>; + pvdd3-supply = <&pp4200_z2>; + pvdd4-supply = <&pp4200_z2>; regulators { mt6319_buck1: vbuck1 { diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index 8e423504ec052..4cb23595d17b4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -217,6 +217,30 @@ domain-supply = <&mt6359_vproc1_buck_reg>; }; +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu4 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu5 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + /* * Geralt is the reference design and doesn't have target TDP. * Ciri is (currently) the only device following Geralt, and its @@ -1149,6 +1173,23 @@ &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <&pp4200_s5>; + vsys-vcore-supply = <&pp4200_s5>; + vsys-vgpu11-supply = <&pp4200_s5>; + vsys-vgpu12-supply = <&pp4200_s5>; + vsys-vpa-supply = <&pp4200_s5>; + vsys-vproc1-supply = <&pp4200_s5>; + vsys-vproc2-supply = <&pp4200_s5>; + vsys-vpu-supply = <&pp4200_s5>; + vsys-vs1-supply = <&pp4200_s5>; + vsys-vs2-supply = <&pp4200_s5>; + vsys-vmodem-supply = <&pp4200_s5>; + vsys-ldo1-supply = <&pp4200_s5>; + vsys-ldo2-supply = <&pp4200_s5>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; }; &postmask0_in { diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index eadf1b2d156f2..40d34b16dc807 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -167,12 +167,22 @@ regulator-name = "pp3300_wlan"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; pinctrl-names = "default"; pinctrl-0 = <&pp3300_wlan_pins>; enable-active-high; gpio = <&pio 143 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_g>; + }; + + /* system wide switching 4.2V power rail */ + pp4200_g: regulator-4v2-g { + compatible = "regulator-fixed"; + regulator-name = "pp4200_g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + vin-supply = <&ppvar_sys>; }; /* system wide switching 5.0V power rail */ @@ -287,6 +297,38 @@ memory-region = <&afe_dma_mem>; }; +&cpu0 { + cpu-supply = <&mt6315_6_vbuck3>; +}; + +&cpu1 { + cpu-supply = <&mt6315_6_vbuck3>; +}; + +&cpu2 { + cpu-supply = <&mt6315_6_vbuck3>; +}; + +&cpu3 { + cpu-supply = <&mt6315_6_vbuck3>; +}; + +&cpu4 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu5 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu6 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + &dsi0 { status = "okay"; }; @@ -514,17 +556,19 @@ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; flash@0 { - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <52000000>; spi-rx-bus-width = <2>; spi-tx-bus-width = <2>; + vcc-supply = <&mt6359_vio18_ldo_reg>; }; }; &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; + memory-region = <&wifi_restricted_dma_region>; pcie0: pcie@0,0 { device_type = "pci"; @@ -539,7 +583,6 @@ wifi: wifi@0,0 { reg = <0x10000 0 0 0 0x100000>, <0x10000 0 0x100000 0 0x100000>; - memory-region = <&wifi_restricted_dma_region>; }; }; }; @@ -609,9 +652,9 @@ "SD_DATA1", "", "", + "BT_KILL_1V8_L", "", - "", - "", + "WIFI_KILL_1V8_L", "", "PCIE_WAKE_ODL", "PCIE_RST_L", @@ -1306,6 +1349,23 @@ &pmic { interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <&pp4200_g>; + vsys-vcore-supply = <&pp4200_g>; + vsys-vgpu11-supply = <&pp4200_g>; + vsys-vgpu12-supply = <&pp4200_g>; + vsys-vpa-supply = <&pp4200_g>; + vsys-vproc1-supply = <&pp4200_g>; + vsys-vproc2-supply = <&pp4200_g>; + vsys-vpu-supply = <&pp4200_g>; + vsys-vs1-supply = <&pp4200_g>; + vsys-vs2-supply = <&pp4200_g>; + vsys-vmodem-supply = <&pp4200_g>; + vsys-ldo1-supply = <&pp4200_g>; + vsys-ldo2-supply = <&pp4200_g>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; }; &pwm0 { @@ -1367,6 +1427,7 @@ reg = <0>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + vin-supply = <&pp4200_g>; }; mt6360_ldo5_reg: regulator@1 { @@ -1374,6 +1435,7 @@ reg = <1>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&pp4200_g>; }; typec { @@ -1427,6 +1489,10 @@ mt6315_6: pmic@6 { compatible = "mediatek,mt6315-regulator"; reg = <0x6 SPMI_USID>; + pvdd1-supply = <&pp4200_g>; + pvdd2-supply = <&pp4200_g>; + pvdd3-supply = <&pp4200_g>; + pvdd4-supply = <&pp4200_g>; regulators { mt6315_6_vbuck1: vbuck1 { @@ -1452,6 +1518,10 @@ mt6315_7: pmic@7 { compatible = "mediatek,mt6315-regulator"; reg = <0x7 SPMI_USID>; + pvdd1-supply = <&pp4200_g>; + pvdd2-supply = <&pp4200_g>; + pvdd3-supply = <&pp4200_g>; + pvdd4-supply = <&pp4200_g>; regulators { mt6315_7_vbuck1: vbuck1 { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index f1ff64a84267c..ef7afc436aefc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -47,6 +47,17 @@ reg = <0 0x40000000 0 0x80000000>; }; + /* system critical LDO 1.8V power rail */ + pp1800_ldo_z2: regulator-pp1800-ldo-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp1800_ldo_z2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&pp3300_z2>; + }; + pp3300_disp_x: regulator-pp3300-disp-x { compatible = "regulator-fixed"; regulator-name = "pp3300_disp_x"; @@ -138,6 +149,53 @@ regulator-boot-on; }; + usb_vbus: regulator-5v0-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb-vbus"; + enable-active-high; + regulator-always-on; + vin-supply = <&pp5000_s5>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xd80000>; + no-map; + }; + + afe_mem: memory@60d80000 { + compatible = "shared-dma-pool"; + reg = <0 0x60d80000 0 0x100000>; + no-map; + }; + + adsp_device_mem: memory@60e80000 { + compatible = "shared-dma-pool"; + reg = <0 0x60e80000 0 0x280000>; + no-map; + }; + }; + + spk_amplifier: rt1019p { + compatible = "realtek,rt1019p"; + label = "rt1019p"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&rt1019p_pins_default>; + sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; + }; + /* Murata NCP03WF104F05RL */ tboard_thermistor1: thermal-sensor-t1 { compatible = "generic-adc-thermal"; @@ -208,54 +266,6 @@ 120000 51 125000 44>; }; - - usb_vbus: regulator-5v0-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - scp_mem: memory@50000000 { - compatible = "shared-dma-pool"; - reg = <0 0x50000000 0 0x2900000>; - no-map; - }; - - adsp_mem: memory@60000000 { - compatible = "shared-dma-pool"; - reg = <0 0x60000000 0 0xd80000>; - no-map; - }; - - afe_mem: memory@60d80000 { - compatible = "shared-dma-pool"; - reg = <0 0x60d80000 0 0x100000>; - no-map; - }; - - adsp_device_mem: memory@60e80000 { - compatible = "shared-dma-pool"; - reg = <0 0x60e80000 0 0x280000>; - no-map; - }; - }; - - spk_amplifier: rt1019p { - compatible = "realtek,rt1019p"; - label = "rt1019p"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&rt1019p_pins_default>; - sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; - }; }; &adsp { @@ -707,8 +717,8 @@ pinctrl-1 = <&mmc1_pins_default>; sd-uhs-sdr50; sd-uhs-sdr104; - vmmc-supply = <&mt_pmic_vmch_ldo_reg>; - vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; + vmmc-supply = <&pp3000_sd>; + vqmmc-supply = <&pp3000_vmc_pmu>; }; &mt6359codec { @@ -763,6 +773,7 @@ spi-max-frequency = <52000000>; spi-rx-bus-width = <2>; spi-tx-bus-width = <2>; + vcc-supply = <&pp1800_ldo_z2>; }; }; @@ -1312,6 +1323,23 @@ &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <&pp4200_z2>; + vsys-vcore-supply = <&pp4200_z2>; + vsys-vgpu11-supply = <&pp4200_z2>; + vsys-vgpu12-supply = <&pp4200_z2>; + vsys-vpa-supply = <&pp4200_z2>; + vsys-vproc1-supply = <&pp4200_z2>; + vsys-vproc2-supply = <&pp4200_z2>; + vsys-vpu-supply = <&pp4200_z2>; + vsys-vs1-supply = <&pp4200_z2>; + vsys-vs2-supply = <&pp4200_z2>; + vsys-vmodem-supply = <&pp4200_z2>; + vsys-ldo1-supply = <&pp4200_z2>; + vsys-ldo2-supply = <&pp4200_z2>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; }; &scp { @@ -1408,20 +1436,22 @@ #size-cells = <0>; }; - mt_pmic_vmc_ldo_reg: regulator@0 { + pp3000_vmc_pmu: regulator@0 { compatible = "google,cros-ec-regulator"; reg = <0>; - regulator-name = "mt_pmic_vmc_ldo"; + regulator-name = "pp3000_vmc_pmu"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; + vin-supply = <&pp4200_z2>; }; - mt_pmic_vmch_ldo_reg: regulator@1 { + pp3000_sd: regulator@1 { compatible = "google,cros-ec-regulator"; reg = <1>; - regulator-name = "mt_pmic_vmch_ldo"; + regulator-name = "pp3000_sd"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3600000>; + vin-supply = <&pp4200_z2>; }; typec { @@ -1455,6 +1485,10 @@ mt6315@6 { compatible = "mediatek,mt6315-regulator"; reg = <0x6 SPMI_USID>; + pvdd1-supply = <&pp4200_z2>; + pvdd2-supply = <&pp4200_z2>; + pvdd3-supply = <&pp4200_z2>; + pvdd4-supply = <&pp4200_z2>; regulators { mt6315_6_vbuck1: vbuck1 { @@ -1472,6 +1506,10 @@ mt6315@7 { compatible = "mediatek,mt6315-regulator"; reg = <0x7 SPMI_USID>; + pvdd1-supply = <&pp4200_z2>; + pvdd2-supply = <&pp4200_z2>; + pvdd3-supply = <&pp4200_z2>; + pvdd4-supply = <&pp4200_z2>; regulators { mt6315_7_vbuck1: vbuck1 { @@ -1584,21 +1622,23 @@ }; &xhci0 { - status = "okay"; - rx-fifo-depth = <3072>; vbus-supply = <&usb_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; }; &xhci2 { - status = "okay"; vbus-supply = <&usb_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; }; &xhci3 { /* MT7921's USB Bluetooth has issues with USB2 LPM */ usb2-lpm-disable; vbus-supply = <&pp3300_wlan>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts index 612336713a64e..0d5a75efb2eed 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -21,3 +21,10 @@ }; }; +&cpu4 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu5 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index 2062506f6cc52..b0c97930a0e6c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -10,7 +10,7 @@ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> */ -#include "mt6359.dtsi" +#include "mt6365.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -285,6 +285,30 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu6 { + cpu-supply = <&mt6319_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6319_vbuck1>; +}; + &disp_dsi0 { #address-cells = <1>; #size-cells = <0>; @@ -445,7 +469,7 @@ mode-switch; orientation-switch; - vcc-supply = <&mt6359_vcn33_1_bt_ldo_reg>; + vcc-supply = <&mt6359_vcn33_1_ldo_reg>; port { it5205_sbu_mux: endpoint { @@ -637,7 +661,7 @@ regulator-always-on; }; -&mt6359_vcn33_2_bt_ldo_reg { +&mt6359_vcn33_2_ldo_reg { regulator-name = "vcn33_2_pmu"; regulator-always-on; }; @@ -695,7 +719,7 @@ regulator-always-on; }; -&mt6359codec { +&mt6365codec { mediatek,mic-type-0 = <1>; /* ACC */ mediatek,mic-type-1 = <3>; /* DCC */ }; @@ -1281,8 +1305,8 @@ interrupt-parent = <&pio>; interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; - mt6359keys: keys { - compatible = "mediatek,mt6359-keys"; + mt6365keys: keys { + compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; mediatek,long-press-mode = <1>; power-off-time-sec = <0>; @@ -1364,6 +1388,50 @@ status = "okay"; }; +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + pmic@6 { + compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + pvdd1-supply = <®_vsys>; + pvdd2-supply = <®_vsys>; + pvdd3-supply = <®_vsys>; + pvdd4-supply = <®_vsys>; + + regulators { + mt6319_vbuck1: vbuck1 { + regulator-name = "dvdd_proc_b"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + vbuck3 { + regulator-name = "avdd2_emi"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + vbuck4 { + regulator-name = "avddq_emi"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + &uart0 { pinctrl-0 = <&uart0_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi index 8da47c9163138..84064511fa0d3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi @@ -58,7 +58,7 @@ regulator-always-on; }; -&mt6359_vcn33_2_bt_ldo_reg { +&mt6359_vcn33_2_ldo_reg { regulator-name = "vcn33_2_pmu"; regulator-always-on; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi index 40b381d4cc35b..9f5a0ec563e8c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi @@ -46,6 +46,20 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmi_ddc>; + hdmi-pwr-supply = <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -283,6 +297,18 @@ remote-endpoint = <&dsi0_in>; }; +&dpi1 { + status = "okay"; +}; + +&dpi1_in { + remote-endpoint = <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint = <&hdmi0_in>; +}; + ð { phy-mode ="rgmii-id"; phy-handle = <ðernet_phy0>; @@ -304,6 +330,35 @@ }; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + &gamma0_out { remote-endpoint = <&postmask0_in>; }; @@ -313,6 +368,26 @@ status = "okay"; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "okay"; +}; + +&hdmi0_in { + remote-endpoint = <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint = <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_vreg_pins>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -531,6 +606,35 @@ }; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dpi1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6359_vproc2_buck_reg>; }; @@ -592,7 +696,7 @@ interrupt-names = "msdc", "sdio_wakeup"; interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>, <&pio 172 IRQ_TYPE_LEVEL_LOW>; - vmmc-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + vmmc-supply = <&mt6359_vcn33_2_ldo_reg>; vqmmc-supply = <&mt6359_vcn18_ldo_reg>; mmc-pwrseq = <&wifi_pwrseq>; status = "okay"; @@ -617,12 +721,12 @@ regulator-boot-on; }; -&mt6359_vcn33_1_bt_ldo_reg { +&mt6359_vcn33_1_ldo_reg { regulator-name = "vcn33_1_pmu"; regulator-always-on; }; -&mt6359_vcn33_2_bt_ldo_reg { +&mt6359_vcn33_2_ldo_reg { regulator-name = "vcn33_2_pmu"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -977,6 +1081,18 @@ }; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &watchdog { pinctrl-names = "default"; pinctrl-0 = <&watchdog_pins>; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index 62c336e215009..edc5539bebde1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -7,7 +7,7 @@ /dts-v1/; #include "mt8195.dtsi" -#include "mt6359.dtsi" +#include "mt6365.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -201,6 +201,22 @@ enable-active-high; regulator-always-on; }; + + /* system wide 4.2V power rail */ + reg_vsys: regulator-vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + }; + + reg_vsys_buck: regulator-vsys-buck { + compatible = "regulator-fixed"; + regulator-name = "vsys_buck"; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vsys>; + }; }; &adsp { @@ -478,7 +494,11 @@ regulator { compatible = "mediatek,mt6360-regulator"; - LDO_VIN3-supply = <&mt6360_buck2>; + BUCK1_VIN-supply = <®_vsys>; + BUCK2_VIN-supply = <®_vsys>; + LDO_VIN1-supply = <®_vsys_buck>; + LDO_VIN2-supply = <®_vsys_buck>; + LDO_VIN3-supply = <®_vsys>; mt6360_buck1: buck1 { regulator-name = "emi_vdd2"; @@ -701,7 +721,7 @@ regulator-always-on; }; -&mt6359_vcn33_2_bt_ldo_reg { +&mt6359_vcn33_2_ldo_reg { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -728,7 +748,7 @@ regulator-max-microvolt = <750000>; }; -&mt6359codec { +&mt6365codec { mediatek,mic-type-0 = <1>; /* ACC */ mediatek,mic-type-1 = <3>; /* DCC */ mediatek,mic-type-2 = <1>; /* ACC */ @@ -1151,8 +1171,8 @@ &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; - mt6359keys: keys { - compatible = "mediatek,mt6359-keys"; + mt6365keys: keys { + compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; mediatek,long-press-mode = <1>; power-off-time-sec = <0>; @@ -1216,8 +1236,8 @@ clocks = <&can_clk>; spi-max-frequency = <20000000>; interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; - xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + vdd-supply = <&mt6359_vcn33_2_ldo_reg>; + xceiver-supply = <&mt6359_vcn33_2_ldo_reg>; }; }; @@ -1238,6 +1258,11 @@ compatible = "mediatek,mt6315-regulator"; reg = <0x6 SPMI_USID>; + pvdd1-supply = <®_vsys>; + pvdd2-supply = <®_vsys>; + pvdd3-supply = <®_vsys>; + pvdd4-supply = <®_vsys>; + regulators { mt6315_6_vbuck1: vbuck1 { regulator-name = "Vbcpu"; @@ -1254,6 +1279,11 @@ compatible = "mediatek,mt6315-regulator"; reg = <0x7 SPMI_USID>; + pvdd1-supply = <®_vsys>; + pvdd2-supply = <®_vsys>; + pvdd3-supply = <®_vsys>; + pvdd4-supply = <®_vsys>; + regulators { mt6315_7_vbuck1: vbuck1 { regulator-name = "Vgpu"; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso index 0389c9cb8581c..ecc9fd27b82d0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso @@ -29,7 +29,7 @@ compatible = "radxa,display-8hd-ad002", "jadard,jd9365da-h3"; reg = <0>; backlight = <&backlight>; - vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + vdd-supply = <&mt6359_vcn33_2_ldo_reg>; vccio-supply = <&mt6360_ldo2>; reset-gpios = <&pio 108 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -57,7 +57,7 @@ interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>; irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>; reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>; - VDDIO-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + VDDIO-supply = <&mt6359_vcn33_2_ldo_reg>; pinctrl-names = "default"; pinctrl-0 = <&touch_pins>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index bf91305e8e4a5..b279eed1bfc3a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -6,7 +6,7 @@ */ #include "mt8195.dtsi" -#include "mt6359.dtsi" +#include "mt6365.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -614,7 +614,7 @@ regulator-always-on; }; -&mt6359_vcn33_2_bt_ldo_reg { +&mt6359_vcn33_2_ldo_reg { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -1034,8 +1034,8 @@ &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; - mt6359keys: keys { - compatible = "mediatek,mt6359-keys"; + mt6365keys: keys { + compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; mediatek,long-press-mode = <1>; power-off-time-sec = <0>; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 340313d48e0f8..263b35f2d09dd 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -192,6 +192,7 @@ CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_MTKSDIO=m CONFIG_BT_QCOMSMD=m CONFIG_BT_NXPUART=m CONFIG_CFG80211=m @@ -514,6 +515,7 @@ CONFIG_MWIFIEX_SDIO=m CONFIG_MWIFIEX_PCIE=m CONFIG_MWIFIEX_USB=m CONFIG_MT7921E=m +CONFIG_MT7921S=m CONFIG_RSI_91X=m CONFIG_WL18XX=m CONFIG_WLCORE_SDIO=m |